A confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.

An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.

A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.

A data sensing circuit includes one or more drive sense circuits operably coupled to a plurality of data sources. The one or more drive sense circuits produces a plurality of digital sense signals regarding the plurality of data sources at an oversampling rate. The data sensing circuit further includes a digital filtering circuit operably coupled to receive, in parallel, at least some of the plurality of digital sense signals and generate, in a serial manner, a plurality of affect values from the least some of the plurality of digital sense signals.

A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.

An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.