H03H2218/06

Subcarrier based adaptive equalization of electrical filtering effects on sub-carrier multiplexed signals
11539447 · 2022-12-27 · ·

Consistent with the present disclosure, the above-described subcarrier noise, which may be characterized as a linear filtering effect, may be reduced or eliminated by providing a first multiple-input multiple output (MIMO) circuits at the transmit end of an optical link and providing a second MIMO circuit at the receive end of the optical link. The first MIMO may include a first plurality of filters, each of which may include a finite-impulse response (FIR) filter having variable coefficients or tap weights that may be changed or adapted to minimize subcarrier noise associated with the modulator, as well as D/A and analog circuitry, at the transmit end of the optical link. In addition, the second MIMO may include a second plurality of filters, each of which may also include an FIR filter having variable coefficients or tap weights that may be changed or adapted to minimized subcarrier noise associated with the optical hybrids, as well as A/D and analog circuitry, at the receive end of the optical link. In one example, a least means square (LMS) technique may be employed to calculate desired coefficients or tap weights whereby an error determined based on the signal detected at the receiver is minimized to update the coefficients of the FIR filters.

DIGITAL FILTER CIRCUIT AND ELECTRONIC DEVICE

A digital filter circuit is described. The digital filter circuit includes a pre-adder circuit, a convolution circuit, and a post-adder circuit. The pre-adder circuit includes a number of n pre-adder sub-circuits, wherein n is an integer greater than or equal to 2. The convolution circuit includes a number of m convolution sub-circuits, wherein m is an integer. The post-adder circuit includes a number of k post-adder sub-circuits, wherein k is an integer greater than or equal to 2. The number m of convolution sub-circuits is greater than the number n of pre-adder sub-circuits of the pre-adder circuit. The number m of convolution sub-circuits is greater than the number k of post-adder sub-circuits of the post-adder circuit. Further, an electronic device is described.

Measuring arrangement and method of measuring electrical signals

A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.

SYSTEM AND METHOD FOR CALIBRATING FILTER MISMATCH IN MULTI-INPUT MULTI-OUTPUT COMMUNICATION SYSTEMS
20200252056 · 2020-08-06 ·

A system and method for calibrating mismatch between the transmit and receive filters of communication nodes in MIMO communications systems. The exemplary calibration algorithm involves two nodes communicating back-and-forth and, based on the received signal, the receiving node calculating an updated calibration matrix and calculating parameters for communicating over the best singular mode (BSM). According to a salient aspect, the updated calibration matrix and the BSM parameters can be calculated as a function of a difference between previous estimates thereof and the current received signal. The calculated BSM parameters and calibration matrix can then be used to transmit a signal back to the other node, which similarly performs the calibration matrix and BSM parameter calculation steps. The calibration algorithm can be repeated by the nodes a suitable number of iterations for each nodes' respective calibration matrix to impose reciprocity on the effective communication channel therebetween.

SUBCARRIER BASED ADAPTIVE EQUALIZATION OF ELECTRICAL FILTERING EFFECTS ON SUB-CARRIER MULTIPLEXED SIGNALS
20190268076 · 2019-08-29 ·

Consistent with the present disclosure, the above-described subcarrier noise, which may be characterized as a linear filtering effect, may be reduced or eliminated by providing a first multiple-input multiple output (MIMO) circuits at the transmit end of an optical link and providing a second MIMO circuit at the receive end of the optical link. The first MIMO may include a first plurality of filters, each of which may include a finite-impulse response (FIR) filter having variable coefficients or tap weights that may be changed or adapted to minimize subcarrier noise associated with the modulator, as well as D/A and analog circuitry, at the transmit end of the optical link. In addition, the second MIMO may include a second plurality of filters, each of which may also include an FIR filter having variable coefficients or tap weights that may be changed or adapted to minimized subcarrier noise associated with the optical hybrids, as well as A/D and analog circuitry, at the receive end of the optical link. In one example, a least means square (LMS) technique may be employed to calculate desired coefficients or tap weights whereby an error determined based on the signal detected at the receiver is minimized to update the coefficients of the FIR filters.

MEASURING ARRANGEMENT AND METHOD OF MEASURING ELECTRICAL SIGNALS
20190257862 · 2019-08-22 ·

A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.

Systems and methods for providing compensation of analog filter bandedge ripple using LPF
10340893 · 2019-07-02 · ·

A method for compensating the bandedge ripple of an analog filter, using a circuit comprising a low pass filter is described. The method comprises receiving, at the analog filter, a plurality of tones of different frequencies from a tone generator, measuring, an amplitude of each tone in the plurality of tones after each tone is processed by the analog filter, storing the measured amplitudes and frequencies in a database, measuring a bandedge ripple by measuring a difference in amplitude between a first tone and a second tone from the plurality of tones, and selecting a low pass filter, from a plurality of low pass filters, based on the measured difference.

RLS-DCD adaptation hardware accelerator for interference cancellation in full-duplex wireless systems

An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter. The iteration signal communicates to continue or conclude; the conclusion indicates determination of a final value of adaptive weights by the core unit.

RLS-DCD ADAPTATION HARDWARE ACCELERATOR FOR INTERFERENCE CANCELLATION IN FULL-DUPLEX WIRELESS SYSTEMS

An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data. In addition, the hardware accelerator unit comprises a convergence detector unit configured to determine a convergence parameter; and a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter. The iteration signal communicates to the calculation unit and the adaptation core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the adaptation core unit.