A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.

Differing from the fact that the amount of register units and adder units arranged in conventional moving average filter must be increased for processing more number of reference input signals, the present invention particularly discloses a moving average low-pass filtering device. The moving average low-pass filtering device comprises a register unit and a filtering and processing unit, and is able to use identical circuit architecture to successfully treat reference input signals with a filtering process even if the number of the reference input signals is alternatively increased. Moreover, after finishing a verification experiment by a simulator, simulation results have proved that, this novel moving average low-pass filtering device still can use identical circuit architecture to complete the filtering process under nearly the same calculation efficiency even though the number of the reference input signals is alternatively increased.

Differing from the fact that the amount of register units and adder units arranged in conventional moving average filter must be increased for processing more number of reference input signals, the present invention particularly discloses a moving average low-pass filtering device. The moving average low-pass filtering device comprises a register unit and a filtering and processing unit, and is able to use identical circuit architecture to successfully treat reference input signals with a filtering process even if the number of the reference input signals is alternatively increased. Moreover, after finishing a verification experiment by a simulator, simulation results have proved that, this novel moving average low-pass filtering device still can use identical circuit architecture to complete the filtering process under nearly the same calculation efficiency even though the number of the reference input signals is alternatively increased.

An apparatus for parallel filtering, including a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. A method is also provided. The apparatus and method have a fast filtering speed, a smaller number of accesses, an improved usage efficiency, a reduced power consumption and a wide application scope.