Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a pair of transistors. The pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

Oscillator calibration circuits and wireless transmitters including oscillator calibration circuits. An oscillator calibration circuit includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session.

A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.