A method for detecting a signal by a signal receiving apparatus is provided. The method includes detecting a part of block diagonal matrices included in a diagonal matrix based on at least one channel impulse response (CIR) for a received signal, detecting remaining block diagonal matrices excluding the part of block diagonal matrices from among block diagonal matrices included in the diagonal matrix, estimating modulation symbols from the received signal based on the diagonal matrix, generating a block diagonal matrix by multiplying one of second matrices included in a first matrix, which is generated by applying a circular extension scheme to a fourth matrix including third matrices, by a fast Fourier transform (FFT) matrix, generating a third matrix for one of the estimated modulation symbols, the third matrix includes vectors for channelization codes, and generating a vector based on the channelization codes or the at least one CIR.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

A high-frequency oscillator includes an electric resonant circuit, and a high-frequency welding system and a method for controlling the frequency uses a high-frequency oscillator, in particular in a high-frequency welding system. The electric resonant circuit includes at least one electronic component having an inductance and at least one capacitor having a capacitance. At least one additional magnetic coil is associated with the electronic component and can electronically influence the inductance of the electronic component.

A high-frequency oscillator includes an electric resonant circuit, and a high-frequency welding system and a method for controlling the frequency uses a high-frequency oscillator, in particular in a high-frequency welding system. The electric resonant circuit includes at least one electronic component having an inductance and at least one capacitor having a capacitance. At least one additional magnetic coil is associated with the electronic component and can electronically influence the inductance of the electronic component.

This disclosure relates to chips, and methods for manufacturing devices, that interact with electromagnetic radiation. A method for manufacturing a device comprises disposing an unpatterned graphene layer on a substrate, which comprises an unpatterned metal layer to form an unpatterned graphene-metal bi-layer attached to a surface of the substrate. The method then comprises patterning the bi-layer through the graphene layer and the metal layer with a design that comprises one or more superimposed trenches. Each of the one or more trenches extend through the graphene layer and the metal layer to provide interaction with electromagnetic radiation.