A network interface for use within a distributed antenna system, the network interface including circuitry configured to: receive a downlink digital communication signal from an external device external to the distributed antenna system, wherein a reference clock is embedded in the downlink digital communication signal; generate a master reference clock for the distributed antenna system using the reference clock embedded in the downlink digital communication signal; convert the downlink digital communication signal into a downlink signal; communicate the downlink signal toward a remote antenna unit within the distributed antenna system; and wherein the distributed antenna system is configured to distribute the master reference clock to various components of the distributed antenna system to keep the various components of the distributed antenna system locked to a single clock, wherein the various components of the distributed antenna system include the remote antenna unit.

A network interface for use within a distributed antenna system, the network interface including circuitry configured to: receive a downlink digital communication signal from an external device external to the distributed antenna system, wherein a reference clock is embedded in the downlink digital communication signal; generate a master reference clock for the distributed antenna system using the reference clock embedded in the downlink digital communication signal; convert the downlink digital communication signal into a downlink signal; communicate the downlink signal toward a remote antenna unit within the distributed antenna system; and wherein the distributed antenna system is configured to distribute the master reference clock to various components of the distributed antenna system to keep the various components of the distributed antenna system locked to a single clock, wherein the various components of the distributed antenna system include the remote antenna unit.

Systems and methods for performing automatic frequency control are provided. Instead of relying on individual frequency tuners for each channel of a multi-channel receiver system, the present subject matter uses a single frequency tuner for receiving each channel of the multi-channel receiver system. A locked demodulator may be designated as a reference demodulator and frequency offset values associated with the reference demodulator may be applied to other demodulators of the multi-channel receiver. These frequency offset values may be used by individual demodulators of each channel for correcting corresponding frequency offsets.

A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

Systems and methods for performing automatic frequency control are provided. Instead of relying on individual frequency tuners for each channel of a multi-channel receiver system, the present subject matter uses a single frequency tuner for receiving each channel of the multi-channel receiver system. A locked demodulator may be designated as a reference demodulator and frequency offset values associated with the reference demodulator may be applied to other demodulators of the multi-channel receiver. These frequency offset values may be used by individual demodulators of each channel for correcting corresponding frequency offsets.

A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

A power electronic converter can utilize exemplary double synchronous unified virtual oscillator control (DSUVOC) logic or circuitry to convert direct current to alternating current that is input into a power grid. An exemplary DSUVOC controller of the present disclosure includes a double synchronous space vector oscillator component, a sequence extraction component, a fault detection component, a pre-synchronization component, a virtual impedance component, a terminal voltage compensation component, and/or an active damping component, wherein the double synchronous unified virtual oscillator controller is capable of controlling a grid following or a grid forming power electronic converter enabling synchronization and fault ride-through under both balanced and unbalanced conditions.