A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

A driving circuit and a driving method are provided. According to embodiments of the present disclosure, a power switch is driven by constant voltage or constant current during different time periods. The power switch is driven by using a first driving current during a Miller platform period, and the power switch is driven by using a second driving current when the Miller platform period ends, where the first driving current is less than the second driving current, so as to optimize EMI, reduce loss and improve efficiency.

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents.

A gate driver includes: an input pin for receiving switching control information from a controller; an output pin for driving a control terminal of a power transistor; a power supply pin for receiving power from an external supply; an input side electrically connected to the input pin; an output side electrically connected to the output pin and the power supply pin; and an isolation structure galvanically isolating the input side and the output side from one another. The output side is configured to transfer a fraction of the power received at the power supply pin to the input side over the isolation structure for powering the input side. The input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure. A power electronic system that includes the gate driver is also described.

A gate drive circuit, which drives a gate of a first transistor, includes a first switch on a high potential side and a second switch on a low potential side connected in series at a second connection node between a high potential end and a low potential end of a series connection structure, constituted of a first voltage source and a second voltage source connected in series at a first connection node; and a third switch and an inductor connected in series between the first connection node and the second connection node. The gate of the first transistor can be electrically connected to the second connection node.

According to one embodiment, electronic circuitry includes a semiconductor switching element; and a driving circuit configured to supply a current to a control terminal of the semiconductor switching element and to adjust a magnitude of the current supplied to the control terminal based on a voltage at the control terminal.