A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The first switch is coupled between a node and a reference voltage. The second switch is coupled between the control terminal of the first transistor and the node. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the node and the output terminal of the inverter circuit.

A method includes detecting a signal on a switching node connected to a power switch, detecting a gate drive voltage of the power switch, during a gate drive process of the power switch, reducing a gate drive current based on a first comparison result obtained from comparing the signal with a first threshold, and during the gate drive process of the power switch, increasing the gate drive current based on a second comparison result obtained from comparing the gate drive voltage with a second threshold.

An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

A hybrid gate driver circuit includes a field effect transistor (FET) drive terminal, a switching node terminal, a transistor, and a capacitor. The transistor includes a first terminal coupled to the FET drive terminal, and a second terminal coupled to ground. The capacitor includes a first terminal coupled to the switching node terminal, and a second terminal coupled to a third terminal of the transistor.

A method of operating a driver circuit includes receiving a data signal at a first input of an amplification circuit; amplifying, using the amplification circuit, the data signal to produce an output signal through an output pin; attenuating, using a feedback network, the output signal to produce a feedback signal; coupling the feedback signal to a second input of the amplification circuit; detecting, using a control circuit, a fault condition; and decoupling, responsive to detecting the fault condition, the feedback signal from the second input of the amplification circuit. In some embodiments, the driver circuit transmits a fault condition signal to an electronic control unit of an automobile.

A switching controller generates control pulses for specifying on/off states of a first transistor and a second transistor. One end of a capacitor is coupled to a switching node. A constant voltage is applied to the other end of the capacitor via a rectifier element. A dead time controller controls a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor.

A power converter includes: a converter including four switching elements in full bridge configuration, the converter converting alternating-current power supplied from an alternating-current power supply into direct-current power; a reactor provided between the alternating-current power supply and the converter; a smoothing capacitor connected between direct-current terminals of the converter; an alternating-current voltage detector detecting an alternating-current voltage output from the alternating-current power supply; an alternating current detector detecting a current flowing through the reactor; and a control circuitry controlling a switching operation of the switching elements. The control circuitry controls the switching elements such that a potential fluctuation due to the switching operation is reduced between a P terminal of the converter and an L terminal of the alternating-current power supply, or between a G terminal of the converter and an N terminal of the alternating-current power supply.