A reverse current suppression circuit for a PMOS transistor, which includes: a gate drive unit, when the source potential of the first PMOS transistor is lower than the drain potential, the gate drive unit making the gate potential of the first PMOS transistor equal to the drain potential, so that the first PMOS transistor comes into a reverse current suppression state; and a substrate switching unit, when the source potential of the first PMOS transistor is lower than the drain potential, the substrate switching unit short-circuiting the substrate of the first PMOS transistor with the drain of the first PMOS transistor. According to the present invention, when the source potential of the PMOS transistor is lower than the drain potential, the PMOS transistor can be controlled to operate in the reverse current suppression state, so that the PMOS transistor can be effectively protected.

A system and method for maintaining electrical stability of a high-voltage transmission power system in response to a fault. The method includes detecting the fault, opening a switch to clear the fault, performing a first pulse test for a predetermined duration of time to determine if the fault is still present, preventing a reclosing operation from occurring if the pulse test indicates that the fault is still present, and allowing the reclosing operation to occur if the first pulse test indicates that the fault is not present. One or more subsequent pulse tests can be performed if the first pulse test is inclusive about the persistence of the fault, where the reclosing operation is prevented from occurring if the pulse tests indicate that the fault is still present and the reclosing operation is allowed if the pulse tests indicate that the fault is no longer present.

Disclosed herein is an overcurrent protection circuit configured to, upon detection of an output current that flows through a switch element reaching a first overcurrent limit value, reduce an overcurrent limit value for the output current from the first overcurrent limit value to a second overcurrent limit value smaller than the first overcurrent limit value.

A shoot-through protection circuit includes a current sensor providing a sensor signal connected to a comparator input via at least a burden resistor. A switch protection circuit including a protection input connected to an output of the comparator and a plurality of outputs. Each of the outputs is connected to a corresponding switch in a plurality of stacked switches. Wherein the switch protection circuit is configured to drive each switch of the plurality of stacked switches open in response to a positive output signal from the comparator.

A semiconductor integrated circuit device includes a control unit configured to control a switching element or an output transistor of a power supply device, a monitor terminal for monitoring an output voltage of the power supply device, a test unit configured to output a test signal to the monitor terminal before activation of the power supply device, and a determination unit configured to determine whether or not the monitor terminal is open, on the basis of a voltage of the monitor terminal when the test unit outputs the test signal to the monitor terminal.

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value. The timer block resets the count value when the output voltage of the power MOS transistor no longer meets the predetermined condition.

A control circuit of a power conversion apparatus is provided with a switch driving unit that drives the upper and lower arm switches; a short circuit control unit that causes the switch driving unit to execute a short circuit control when a failure occurs in the system, the short circuit control turning an ON side switch to an ON state and turning an OFF side switch to an OFF state; a checking unit that executes a checking process to check whether the short circuit control is able to perform correctly; and a protection control unit that causes the switch driving unit to execute a protection control when a failure occurs on either the upper arm switch or the lower arm switch, the protection control turning the switch where the failure occurs to an OFF state. The control circuit enables the protection control during execution of the checking process.

An electronic fuse circuit includes an electronic switch with a load current path coupled between an output node and a supply node and that connects or disconnects the output node and the supply node in accordance with a drive signal. The circuit includes a control circuit to generate the drive signal based on an input signal. A monitoring circuit is included in the control circuit to receive a current sense signal representing the load current passing through the load current path and to determine a first protection signal based on the current sense signal and a wire parameter. The first protection signal is indicative of whether to disconnect the output node from supply node. The control circuit changes from normal mode to idle mode when the load current is below a given current threshold and another criterion is fulfilled.