A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

A turn-off protection circuit and a turn-off protection method for a switch unit. The switch unit may include a first set of switching devices coupled between a first circuit node and an output node, and a second set of switching devices coupled between a second circuit node and the output node. The turn-off protection circuit may compare a first circuit node potential at the first circuit node and/or a second circuit node potential at the second circuit node with a switch node potential at the output node to detect a the flow direction of the a freewheeling current when the switch unit is turned off, and turn on and maintain the first set of switching devices or the second set of switching devices on depending on the flow direction of the freewheeling current until the freewheeling current is reduced to a predetermined safe current threshold.

The disclosure relates to a switched capacitor converter with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include a switched capacitor converter (100), SCC, comprising a plurality of gate driver circuits (101a-d, 200, 300) arranged to provide a gate voltage signal to a respective power FET (102a-d) in response to a respective input switching signal (sw1_in, sw2_in, sw3_in, sw4_in, IN), wherein each gate driver circuit (101a-d, 200, 300) comprises a first gate driver module (206) and a second gate driver module (207), the gate driver circuit (101a-d, 200, 300) configured to operate in: a first mode in which the first gate driver module (206) provides the gate voltage signal to a respective power FET (102a-d, 205) in response to an input switching signal (IN) at an input (203) of the first gate driver module (206) causing the gate voltage signal to switch between first and second voltage rails (201, 202) by operation of first and second switches (208, 209) connected between the pair of voltage rails (201, 202); and a second mode in which, in response to enabling of a current limit switching signal (climit_en), the first gate driver module disables switching of one of the first and second switches (208, 209) and the second gate driver module (207) operates to limit a current provided to the respective power FET (102a-d, 205).

A method for active gate driving a switching circuit, wherein: a characteristic of a waveform controlled by the switching circuit is represented by a function mapping an input variable to an output metric, and wherein: the input variable comprises: a design variable having a first set of possible values; and an environmental variable having a second set of possible values, wherein the environmental variable is observable but not controllable. The method comprising: performing Bayesian optimisation on the function to generate a model of the function, wherein a next value of the design variable for evaluating the function is selected based on values of an acquisition function associated with a predicted value of the environmental variable; determining a first value of the design variable that optimises the model of the function; and controlling the switching circuit according to the first value of the design variable.

A signal detection circuit includes: a voltage dividing circuit having at least a first pair of voltage dividing capacitors connected in series for dividing an input voltage and configured to output a divided voltage, and a detection circuit configured to detect the divided voltage. The first pair of voltage dividing capacitors are included in one semiconductor device. The semiconductor device includes: (i) a semiconductor substrate, (ii) a first conductor layer, (iii) a first dielectric layer, (iv) a second conductor layer, (v) a second dielectric layer, (vi) a third conductor layer, and (vii) a short-circuit portion configured to short-circuit the first conductor layer and the semiconductor substrate.

A power converter apparatus comprises a set of switching elements communicatively coupled with a set of gate drive circuits. Each gate drive circuit is configured to provide a respective drive signal to a corresponding switching element, each switching element being switchably responsive to the respective drive signal. The apparatus includes a controller module configured to control an output state of the power converter, and selectively change one of a respective gate resistance and a respective gate current of a corresponding subset of the gate drive circuits based on the output state of the power converter.

A driver circuit controls a first switch element. A first resistor is connected between the driver circuit and the first switch element. A second switch element is connected to the first switch element. An overcurrent detector circuit controls the second switch element based on an overcurrent current flowing through the first switch element. A second resistor is connected between the overcurrent detector circuit and the second switch element. The first and second resistor is set such that a turn-off time of the first switch element when the second switch element is turned on by the overcurrent detector circuit is longer than a turn-off time of the first switch element when the first switch element is turned off by the driver circuit.

Methods and apparatus to provide an adaptive gate driver for switching devices are disclosed. An example apparatus includes an electrical switch to drive an electrical system; a condition characterizer to select a drive strength based on a first system parameter corresponding to the electrical system, the first system parameter including at least one of an input voltage corresponding to the electrical switch, an output current corresponding to the electrical switch, or a process variation of the electrical switch; and a driver to generate an output having a current corresponding to the selected drive strength.

For example, a semiconductor device includes an output electrode to be connected to an inductive load, a ground electrode to be connected to a ground terminal, first and second transistors connected in parallel between the output and ground electrodes, an active clamp circuit connected to the gate of the first transistor, and a gate control circuit to control the gates of the first and second transistors to keep the first and second transistors on in a first operation state and off in a second operation state. After a transition from the first operation state to the second, before the active clamp circuit operates, the gate control circuit short-circuits between the gate and source of the second transistor.