Passive Ethernet by-pass switches, methods of using the same, and systems including the passive Ethernet by-pass switches include a first connection configured to be coupled to a first Ethernet port, a second connection configured to be coupled to a second Ethernet port, and switching circuitry including at least one internal switch operable to allow network communication between the first connection, the second connection, and at least one Ethernet controller, the at least one internal switch including a depletion mode transistor operable to bridge the first connection to the second connection to establish communication between the first connection and the second connection.

An image display apparatus is disclosed. The image display according to an embodiment of the present disclosure includes a signal processing device including a first logic circuit to process a first voltage range of a voltage level of the input signal, a second logic circuit to process a second voltage range of the voltage level of the input signal, higher than the first voltage range, and a protection control circuit including a protection switch and a protection controller for controlling the protection switch, wherein the protection switch is turned on based on the protection controller being turned off or powered down. Accordingly, a breakdown phenomenon can be reduced in case of power off or power down.

A printing apparatus includes a connector configured to receive supply of first power from outside, a switch circuit configured to supply the first power to a regulator, a latch circuit configured to control the switch circuit, a power switch configured to hold the latch circuit in a predetermined state, a controller configured to hold the latch circuit in the predetermined state and to detect an operation of the power switch, and a storage configured to store setting information. In response to supply of the first power to the connector, the latch circuit is configured to, when supplied with the first power and when the predetermined state is a first state, switch on the switch circuit to supply the first power to the regulator. The regulator is configured to generate second power based on the supplied first power and to supply the second power to the controller and the storage. The controller is configured to, when the setting information in the storage is valid, maintain the latch circuit in the first state without performing detection of the operation of the power switch.

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

A switch device includes a phase change switch and a memory for storing a target state of the phase change switch. A controller determines a phase state of the phase change switch, and, if the state of the phase change switch does not correspond to the target state, controls a heater of the phase change switch to change the state of the phase changes switch to the target state.

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

A circuit may include an electronic switch that has a load current path coupled between an output node and a supply node and that is configured to connect or disconnect the output node and the supply node in accordance with a drive signal. Further, the circuit includes a monitoring circuit that is configured to receive a current sense signal, which represents the load current passing through the load current path, and that is further configured to determine a protection signal based on the current sense signal, a state of the monitoring circuit, and at least one wire parameter. The wire parameter characterizes a wire that is—during operation—connected to the output node, and the protection signal is indicative of whether to disconnect the output node from supply node. Further, the circuit includes a protection circuit connected to the monitoring circuit.

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.