A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.

A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.

A drive circuit of a voltage-controlled power semiconductor element, including first to fourth switching elements, first and second delay circuits, an overcurrent detection circuit, a slow shutdown detection circuit and a flip-flop. The first switching element turns on upon receiving an off signal. The second switching element is turned on by the first delayed signal generated by the first delay circuit. The third switching element turns on upon receiving a second delayed signal generated by the second delay circuit through the flip-flop. The fourth switching element is turned on by the slow shutdown detection signal generated by the slow shutdown detection circuit. The first to fourth switching elements extract electric charges from the gate terminal of the voltage-controlled power semiconductor element, with first to fourth extracting capabilities, respectively. The first and fourth extracting capabilities are larger than the third extracting capability and smaller than the second extracting capability.

A semiconductor element drive device is provided to solve a problem that because a case of a change in the temperature of the semiconductor element or a current flowing through the semiconductor element is not take into consideration, switching loss and noise cannot be reduced sufficiently. In accordance with input sensing information (temperature T, current I), a timing control unit 3 outputs a delay signal Q to control timing of driving a current increasing circuit 5 so that a reduction of switching loss of an IGBT 101 is maximized. When the IGBT 101 is in turn-on mode or turn-off mode, the current increasing circuit 5 outputs a drive signal in response to the delay signal Q delayed by a given time from output of the drive instruction signal P. In this way, the current increasing circuit 5 increases the current that causes the gate capacitor of the IGBT 101 to be charged/discharged in response to the delay signal Q, thereby increasing a switching speed to reduce switching loss.

A driver circuit for driving a switching device having a control electrode. The driver circuit includes an ON circuit configured to turn on the switching device in response to a first drive signal, and an OFF circuit configured to discharge a parasitic capacitance of the control electrode of the switching device with a constant current, to turn off the switching device, in response to a second drive signal.

A drive device for a voltage-controlled semiconductor element. The drive device includes: a short-circuit current detection circuit which detects a short-circuit current flowing through the voltage-controlled semiconductor element; a timer circuit which outputs a time setting signal indicative of a determined time, responsive to the short-circuit current detection circuit detecting the short-circuit current; and a control power source voltage variable circuit which receives a power supply voltage applied to the drive device, decreases the power supply voltage for a period for which the control power source voltage variable circuit receives the time setting signal from the timer circuit, to thereby obtain a stepped-down voltage, and outputs the stepped-down voltage as a control power source voltage.

A power module, including a high-side switching element and a low-side switching element connected to form a half bridge circuit, a high-side drive circuit which drives the high-side switching element, a low-side drive circuit which drives the low-side switching element, and a high-side current detection circuit which detects a current of the high-side switching element. The high-side drive circuit includes a high-side variable delay circuit which adjusts, according to a value detected by the high-side current detection circuit, a length of a high-side delay time from a time when a signal is inputted to the high-side drive circuit to a time when the high-side switching element is driven.

An electric assembly includes an insulated gate bipolar transistor device, a wide-bandgap transistor device electrically connected in parallel with the bipolar transistor device and a control circuit. The control circuit is electrically coupled to a gate terminal of the bipolar transistor device and to a control terminal of the wide-bandgap transistor device. The control circuit is configured to turn on the bipolar transistor device and to turn on the wide-bandgap transistor device at a predefined turn-on delay with respect to a turn-on of the bipolar transistor device.