A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

A controlling circuit includes a pulse width modulation (PWM) circuit, a level shifter having a current source therein, a capacitor connected to a current source, an overcurrent protection circuit connected to the level shifter, and a controlling circuit configured to enable or disable a function of overcurrent protection of the overcurrent protection circuit within designated time. The controlling circuit includes a switch device. An input of the switch device connected to an output terminal of the capacitor, and an output terminal of the switch device connected to a controlling terminal of the overcurrent protection circuit.

A controlling circuit includes a pulse width modulation (PWM) circuit, a level shifter having a current source therein, a capacitor connected to a current source, an overcurrent protection circuit connected to the level shifter, and a controlling circuit configured to enable or disable a function of overcurrent protection of the overcurrent protection circuit within designated time. The controlling circuit includes a switch device. An input of the switch device connected to an output terminal of the capacitor, and an output terminal of the switch device connected to a controlling terminal of the overcurrent protection circuit.

High voltage high power pulsed power switches relating to a laser triggered multi-stage vacuum switch. The laser triggered multi-stage vacuum switch has laser triggered vacuum gap, multi-stage self-breakdown vacuum gaps and trigger system. Multi-stage self-breakdown vacuum gaps are fixed on the top of laser triggered vacuum gap by connector. The grading ring is sheathed outside of upper insulation shell. By adopting the series connected laser triggered vacuum gap and multi-stage self-breakdown vacuum gaps, with the synergy of two type vacuum gaps, application of laser triggered multi-stage vacuum switch in the high voltage, high power, high repetitive frequency pulsed power system can be realized. With multiple laser beams shot onto multiple targets, more initial plasma can be generated as the irradiation area of laser on target surfaces is enlarged, and the trigger performances of laser triggered multi-stage vacuum switch can be enhanced.

In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

High voltage high power pulsed power switches relating to a laser triggered multi-stage vacuum switch. The laser triggered multi-stage vacuum switch has laser triggered vacuum gap, multi-stage self-breakdown vacuum gaps and trigger system. Multi-stage self-breakdown vacuum gaps are fixed on the top of laser triggered vacuum gap by connector. The grading ring is sheathed outside of upper insulation shell. By adopting the series connected laser triggered vacuum gap and multi-stage self-breakdown vacuum gaps, with the synergy of two type vacuum gaps, application of laser triggered multi-stage vacuum switch in the high voltage, high power, high repetitive frequency pulsed power system can be realized. With multiple laser beams shot onto multiple targets, more initial plasma can be generated as the irradiation area of laser on target surfaces is enlarged, and the trigger performances of laser triggered multi-stage vacuum switch can be enhanced.

A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

A controlling circuit includes a pulse width modulation (PWM) circuit, a level shifter having a current source therein, a capacitor connected to a current source, an overcurrent protection circuit connected to the level shifter, and a controlling circuit configured to enable or disable a function of overcurrent protection of the overcurrent protection circuit within designated time. The controlling circuit includes a switch device. An input of the switch device connected to an output terminal of the capacitor, and an output terminal of the switch device connected to a controlling terminal of the overcurrent protection circuit.