Systems and apparatuses include a circuit structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery, inhibit communication between the real-time-clock battery and a controller when a first voltage is received from the vehicle battery, and provide a communication from the real-time-clock battery to the controller when the first voltage is not received.

Systems and apparatuses include a circuit structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery, inhibit communication between the real-time-clock battery and a controller when a first voltage is received from the vehicle battery, and provide a communication from the real-time-clock battery to the controller when the first voltage is not received.

There is provided a current detection circuit including: a current detection unit that detects a control current flowing between a control terminal of a semiconductor element of voltage-controlled type having a current detection terminal, and a drive circuit; an overcurrent detection unit that detects an overcurrent based on a result of comparing a sense voltage with a sense reference voltage, the sense voltage corresponding to a sense current flowing through the current detection terminal; and an adjustment unit that adjusts the sense reference voltage based on a detection result of the current detection unit.

There is provided a current detection circuit including: a current detection unit that detects a control current flowing between a control terminal of a semiconductor element of voltage-controlled type having a current detection terminal, and a drive circuit; an overcurrent detection unit that detects an overcurrent based on a result of comparing a sense voltage with a sense reference voltage, the sense voltage corresponding to a sense current flowing through the current detection terminal; and an adjustment unit that adjusts the sense reference voltage based on a detection result of the current detection unit.

Provided is a switching apparatus, including: a first semiconductor switching device of IGBT, and a second semiconductor switching device of a different type from IGBT, which are electrically connected in parallel; and a control unit configured to turn on the second semiconductor switching device before the first semiconductor switching device, wherein a maximum rated current of the second semiconductor switching device is greater than a maximum rated current of the first semiconductor switching device.

Provided is a switching apparatus, including: a first semiconductor switching device of IGBT, and a second semiconductor switching device of a different type from IGBT, which are electrically connected in parallel; and a control unit configured to turn on the second semiconductor switching device before the first semiconductor switching device, wherein a maximum rated current of the second semiconductor switching device is greater than a maximum rated current of the first semiconductor switching device.

A semiconductor device including: NMOS transistors respectively having the drains, which are connectable to respective second terminals of boot capacitors of which respective first terminals are connectable to respective nodes at which high-side transistors and the low-side transistors are connected together, and the sources, which are electrically connectable to an application terminal for a supply voltage; and controllers driving respective gates of the plurality of NMOS transistors. When the high-side transistor for a first channel is kept off by the driver for the first channel, the high-side transistor for a second channel, which is different from the first channel, is kept on by the driver for the second channel. The controller for the first channel feeds a drive voltage based on the boot voltage for the second channel to the gate of the NMOS transistor for the first channel to keep on the NMOS transistor.

A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

A signal transmission device relating to a technique disclosed in the specification of the present application includes: an isolation transformer; an input-side circuit connected to an input side of the isolation transformer; and an output-side circuit connected to an output side of the isolation transformer. The output-side circuit includes a first differential circuit having a first input and a second input connected to the first terminal and the second terminal respectively. A reference potential of the first differential circuit is connected to the second terminal.