Bias supplies, plasma processing systems, and associated methods are disclosed. One bias supply comprises a bidirectional switch configured to enable bidirectional control of current. A controller is configured to control a direction of current through the bidirectional switch over a full current cycle, the full current cycle comprising a first half current cycle and a second half current cycle, the first half current cycle comprising positive current flow, starting from zero current that increases to a positive peak value and then decreases back to zero. The second half current cycle comprises negative current flow, starting from zero current that increases to a negative peak value and then decreases back to zero current to cause an application of the periodic voltage between the output node and the return node.

Bias supplies, plasma processing systems, and associated methods are disclosed. One bias supply comprises a bidirectional switch configured to enable bidirectional control of current. A controller is configured to control a direction of current through the bidirectional switch over a full current cycle, the full current cycle comprising a first half current cycle and a second half current cycle, the first half current cycle comprising positive current flow, starting from zero current that increases to a positive peak value and then decreases back to zero. The second half current cycle comprises negative current flow, starting from zero current that increases to a negative peak value and then decreases back to zero current to cause an application of the periodic voltage between the output node and the return node.

According to one embodiment, a semiconductor device includes a first switch element including a first end to which a first voltage is applied, and a second end and a gate electrically coupled to a first node, a second switch element including a first end to which a second voltage is applied, and a second end and a gate electrically coupled to the first node, a third switch element including a first end to which the second voltage is applied, a second end electrically coupled to a second node, and a gate coupled to the first node, a fourth switch element including a gate coupled to the second node, and a first terminal electrically coupled to a first end of the fourth switch element and outputting a signal based on a voltage of the second node.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

The present disclosure provides a battery protection device and a chip therein. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to a third logic control signal. The select circuit is configured to select the second or third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

The present disclosure provides a battery protection device and a chip therein. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to a third logic control signal. The select circuit is configured to select the second or third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.

In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

A vehicle analog comparator circuit for communication interfaces designed to detect an actuation of an actor. The circuit comprises a unit for producing a supply voltage for supplying the actor, a unit for producing a reference voltage to be compared with the supply voltage, a transistor input stage, a node point EDMx between the actor, the unit for producing a supply voltage and the transistor input stage, and a digital evaluation unit to process the output signal from the transistor input stage such that whether or not the actor is actuated is detected. The transistor input stage comprises a transistor circuit with a first transistor is connected to the node point EDMx, and a second transistor connected to the reference voltage. A collector resistance for limiting the collector current of the second transistor, as well as a base resistance for the two transistors. Alternatively, a current mirror is provided.