The present disclosure provides a system and method for reception of BMC data in USB PD communication. The system comprises an analog block and a digital block with the digital block further comprising an idle detection mechanism, and a digital controller for rejecting noise and auto correcting of received BMC signal. The BMC data is typically processed by means of varied functions such as comparison by a threshold comparator on the analog block with programmable reference, and other components of the digital block so as to realize aspects such as noise filtering of BMC data by changing the reference dynamically based on comparison of the width of threshold comparator output signal with average signal widths which is computed during the preamble phase of USB PD communications.

A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (PO) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

An arbiter for use with a plurality of request signals is presented. The arbiter includes a sequence identifier to identify an order between the plurality of request signals. The arbiter provides a plurality of output signals in which each output signal is associated with a request signal. When the request signals are provided in a sequential order the output signals are provided in the identified sequential order. When the request signals are provided substantially at the same time the output signals are provided in an arbitrary sequential order. A corresponding signal arbitration method and an electronic circuit comprising the arbiter are also presented.

A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.

A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.

An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

This patent document provides implementations and examples of circuits and devices based on low-energy consumption semiconductor structures exhibiting multi-valued states. In one aspect, a semiconductor device is configured to comprise: a multi-layer structure forming a magnetoelectric or multiferroic system to include a ferromagnetic, magnetostrictive layer that exhibits a biaxial magnetic anisotropy and an underlying metal structure exhibits a spin Hall effect to provide a conversion between electrical energy and magnetic energy with more than two distinctive magnetic states.