A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

The off-chip driving (OCD) device includes a signal transition detector, a front-end driver, a first main driver, a second main driver, a first resistance provider and a second resistance provider. The signal transition detector is used to detect a transition status of an input signal to generate decision information. The front-end driver generates control signals according to the decision information, and generates driving signals according to the input signal. The first main driver and the second main driver generate an output signal to a pad according to the driving signals. The first resistance provider adjusts a first resistance between the first main driver and the pad according to a first control signal. The second resistance provider adjusts a second resistance between the second main driver and the pad according to a second control signal.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

An output driver includes a first pre-driver circuit, a first driver circuit, a second pre-driver circuit, a second driver circuit, and a feedback network. The first pre-driver circuit pre-drives a first data input signal to generate a first pre-driving output signal. The first driver circuit drives the first pre-driving output signal to generate a first data output signal. The second pre-driver circuit pre-drives a second data input signal to generate a second pre-driving output signal, wherein the first data input signal and the second data input signal are a differential input of the output driver. The second driver circuit drives the second pre-driving output signal to generate a second data output signal. The feedback network performs a latching operation upon the first pre-driving output signal and the second pre-driving output signal according to the first data output signal and the second data output signal.

Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

A semiconductor apparatus may include: a command generation circuit configured to generate a first internal command signal and a second internal command signal, which are sequentially activated on the basis of a data command signal for a data driving operation; an impedance setting circuit enabled on the basis of the first internal command signal, and configured to set impedance into which a reference resistance is reflected; and a data driving circuit enabled on the basis of the second internal command signal, and configured to perform the data driving operation on the basis of the set impedance.

A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

An impedance calibration circuit, an impedance calibration method, and a memory are provided. The impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module. The parameter module is configured to perform environment detection processing and output an environment parameter signal; the initial value generation module is configured to receive the environment parameter signal, and output an initial calibration value based on the environment parameter signal when the calibration instruction signal is received; and the calibration module is configured to receive the initial calibration value, and perform impedance calibration processing based on the initial calibration value when the calibration instruction signal is received.

An enable control circuit and a semiconductor memory are provided. The enable control circuit includes: a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value; a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.