A safety switching device for fail-safely disconnecting an electrical load has an input part for receiving a safety-relevant input signal, a logic part for processing the at least one safety-relevant input signal, and an output part. The output part has a relay coil and four relay contacts. The first and second relay contacts are arranged electrically in series with one another. The third and fourth relay contacts are also arranged electrically in series with one another. The first and the third relay contacts are mechanically coupled to each other and form a first group of positively driven relay contacts. The second and the fourth relay contacts are mechanically coupled to each other and form a second group of positively driven relay contacts. The logic part redundantly controls the first and the second groups of positively driven relay contacts to selectively allow, or to interrupt in a fail-safe manner, a current flow to the electrical load, depending on the safety-relevant input signal. The relay coil is electromagnetically coupled to the first and second groups of positively driven relay contacts so that the logic part can control the relay contacts together via a single relay coil.

Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

The invention relates to a sensor circuit for a device performing a safety function, comprising at least two sensors, at least two comparison circuits, each of the comparison circuits being assigned to one of the sensors, and a linking unit for combining logic states (L=0, L=1) of comparison circuit outputs of the comparison circuits to form a circuit output signal, the sensor circuit being configured to scale the comparison circuit output value of at least a first one of the comparison circuits and to feed it back to a measurement input or a reference input of at least a second one of the comparison circuits so that, when the comparison circuit output of the first comparison circuit transitions between the logic states (L=0, L=1), the difference between the measurement signal and the reference signal of the second comparison circuit is reduced or the sign of the difference between the measurement signal and the reference signal of the second comparison circuit is reversed.

The invention further relates to a device comprising the sensor circuit and a method for processing measurement values from sensors.

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

A semiconductor device includes: a first line; a second line that is not connected to the first line and is provided to transfer a signal having a level same as a level of a signal transferred through the first line; and another line different from the first line and the second line. In a line layer, a distance between the first line and the second line is longer than a distance between the first line and the other line, and is longer than a distance between the second line and the other line.

A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.

A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.

A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.