A transformer includes a primary winding and a secondary winding. A transmitting circuit is coupled to a primary winding of a transformer and supplies a current signal to the primary winding with a polarity that changes in response to a change of the input signal level. A latch circuit is arranged such that its set terminal is coupled to one end of the secondary winding of the transformer, and its reset terminal is coupled to the other end of the secondary winding of the transformer. A first switch is arranged between a common voltage node at which a common voltage occurs and the set terminal. When the output of the latch circuit is high, the first switch is turned on. A second switch is arranged between the common voltage node and the reset terminal. When the output of the latch circuit is low, the second switch is turned on.

A primary transmitter drives a primary-side input of an isolation barrier in response to a transition of an input signal. A secondary receiver generates an output signal having a logical value that corresponds to a signal that occurs at a secondary-side output of the isolation barrier. A secondary transmitter drives a secondary-side input of the isolation barrier based on the output signal. A primary receiver generates a return signal having a logical value that corresponds to a signal that occurs at a primary-side output of the isolation barrier. The primary transmitter repeatedly drives the primary-side input of the isolation barrier until the logical value of the input signal matches that of the return signal.

The present application provides a differential signal interface and a display device adopting the differential signal interface. A plurality of different differential signals are transmitted between a transmitting end and a receiving end of the differential signal interface by a plurality of differential pairs. A plurality of moderating modules are disposed between the transmitting end and the receiving end. Each moderating module is connected to a corresponding differential pair and is configured to adjust the impedance of the transmitting end and/or the receiving end such that the impedance of the transmitting end and/or the receiving end matches the impedance of the corresponding differential pair.

Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.

The circuit device includes a first MOS transistor of a first conductivity type a source of which is coupled to a first power supply voltage node, a second MOS transistor of a second conductivity type a source of which is coupled to a second power supply voltage node, a first variable resistance circuit which is coupled between a drain of the first MOS transistor and an output node, and which includes a first switch, and a second switch coupled between the drain of the first MOS transistor and the second power supply voltage node. The control circuit performs control of making the first switch OFF and making the second switch ON when the clock signal fails to be output from the output node, and making the first switch ON and making the second switch OFF when the clock signal is output from the output node.

Circuits and methods to mitigate or eliminate potentially damaging events (e.g., damaging current spikes from in-rush current, charge transfer current, short circuits, etc.) in DC-DC power converters. Embodiments enable dynamic switching of conversion ratios in reconfigurable power converters while under load without turning off the power converter circuitry or suspending switching of the charge pump power switches. Embodiments selectively increase the ON resistance, R.sub.ON, for at least some power FETs in a power converter by actively controlling the driver voltage to the gates of the power FETs. During normal operation, the power FET driver voltage may be set to overdrive the FET gate to lower R.sub.ON to a desired level that allows high current flow. For other scenarios, the power FET driver voltage may be reduced so as to increase R.sub.ON while ON and thus impede current flow to provide protection against potentially damaging events.

The invention relates to a digital isolator comprising a logic module (20) for receiving an input signal D, and providing command signals (41, 42) to sawtooth modulators. A first sawtooth modulator provides a first sawtooth signal at a node A1 comprising a fast rising edge triggered by a rising edge of a control signal, followed by a slow falling edge, when D equals 1 and comprises a fast falling edge triggered by a rising edge of a control signal, followed by a slow rising edge, when D equals 0. A second sawtooth modulator provides a second sawtooth signal at node A2, inverted with respect to first sawtooth signal. Isolation capacitors (61, 62) are connected to nodes A1 and A2 and are used as isolation barrier and as part of a high-pass filter together with dipoles Z1 and Z2. Threshold comparators (121, 122) provide the output signals S and R. Based on these S and R output signals, the input signal D referred to ground G1 can be regenerated versus a ground G2 using for example SR logic gate, low pass filters or peak detectors.

Various embodiments relate to a transmit driver circuit, including: a first node connected to a first differential output; a first transistor connected in series with a first resistor, wherein the series connected first transistor and first resistor are connected between a source voltage and the first node; a second transistor connected in series with a second resistor, wherein the series connected second transistor and second resistor are connected between the first node and a ground; a second node connected to a second differential output; a third transistor connected in series with a third resistor, wherein the series connected third transistor and third resistor are connected between the source voltage and the second node; a fourth transistor connected in series with a fourth resistor, wherein the series connected fourth transistor and fourth resistor are connected between the second node and the ground; a first differential input connected to the gate of the first transistor and the gate of the fourth transistor; and a second differential input connected to the gate of the second transistor and the gate of the third transistor, wherein the first transistor, second transistor, third transistor, and fourth transistor are NMOS transistors.

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Devices and/or computer-implemented methods to facilitate ZZ cancellation between qubits are provided. According to an embodiment, a device can comprise a coupler device that operates in a first oscillating mode and a second oscillating mode. The device can further comprise a first superconducting qubit coupled to the coupler device based on a first oscillating mode structure corresponding to the first oscillating mode and based on a second oscillating mode structure corresponding to the second oscillating mode. The device can further comprise a second superconducting qubit coupled to the coupler device based on the first oscillating mode structure and the second oscillating mode structure.