A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

An integrated circuit comprises a power input, digital logic circuitry, a plurality of charge stores, and obscuring circuitry. The charge stores are configured to receive power from the power input, are distributed through the digital logic circuitry and are capable of providing power to the digital logic circuitry. The obscuring circuitry is configured to obscure electromagnetic emissions associated with flow of current in current loops between the plurality of charge stores and the digital logic circuitry by switching between a plurality of different charge store activation patterns, wherein each charge store activation pattern describes a different selection of one or more of the plurality of charge stores providing power to the digital logic circuitry at a given time.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding sub array of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

A personal laboratory includes a self-contained, miniaturized, portable kit that provides for design, testing, and automated assembling, dissembling, and reassembling of a physical system (rather than a simulation) with flexibility as to the variety of configurations of components that may be designed and assembled, and easy integration of complex components. The personal laboratory includes a reconfigurable system, the reconfigurable system includes a plurality of functional components, and a plurality of connectors configured for operatively connect respective functional components to other functional components; a stimulus generator configured to apply a stimulus to the reconfigurable system; and a measurement system configured to measure a response to the applied stimulus generated by the reconfigurable system. In the context of electronic circuits, the reconfigurable system is a reconfigurable circuit, the functional components are circuit elements and the connectors are electrical connectors.

Techniques are disclosed for power conservation. A plurality of processing elements and a plurality of instructions are configured. The plurality of processing elements is controlled by instructions contained in a plurality of circular buffers. The plurality of processing elements can comprise a dataflow processor. A first processing element, from the plurality of interconnected processing elements, is set into a sleep state by a first instruction from the plurality of instructions. The first processing element is woken from the sleep state as a result of valid data being presented to the first processing element. A subsection of the plurality of interconnected processing elements is also set into a sleep state based on the first processing element being set into a sleep state. At least one circular buffer from the plurality of circular buffers remains awake while the first processing element is in the sleep state, and the at least one circular buffer provides for data steering through a reconfigurable fabric.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.