In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.

The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.

A receiver includes the following: a signal receiving circuit, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving circuit is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting circuit, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal.

The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A device for synchronous serial data transmission over a differential data channel and a differential clock channel includes an interface controller having a clock generator, data controller, clock transmitter block and data receiver block. The clock generator generates a transmit clock signal which, during a data transmission cycle, includes a clock pulse train having a period. The clock generator is suitably configured such that, for data transmission cycles in a dynamic operating state in which a maximum occurring differential voltage of a differential clock signal is lower than a maximum differential voltage of the clock transmitter block, the clock generator sets a duration of a first clock phase of a first clock period of the clock pulse train to be longer than a first clock phase of following clock periods and shorter than a time duration required to reach the maximum differential voltage.