An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

A semiconductor device according to an embodiment of the present disclosure includes an output driver including a first variable resistor element, a replica circuit including a second variable resistor element and having the same configuration as the output driver, a first wiring line coupled to an output end of the replica circuit; a second wiring line electrically coupled to a first external terminal; and a comparator that compares a voltage of the first wiring line with a voltage of the second wiring line.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.

Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.

There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.