A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.

Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

A semiconductor device includes: an arithmetic circuit that repeats an operation related to a cryptographic processing for the predetermined number of rounds; a holding circuit that holds data related to the number of rounds of an operation of the arithmetic circuit; a judgement circuit that determines whether the number of rounds is the predetermined number of rounds; and an output buffer circuit that outputs the arithmetic result data of the arithmetic circuit when the judgement circuit determines that the number of rounds is the predetermined number. It is configured to duplicate the holding circuit, and not to output the arithmetic result data when two outputs of the duplicated holding circuit are not matched.

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.