A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.

A transformer includes a primary winding and a secondary winding. A transmitting circuit is coupled to a primary winding of a transformer and supplies a current signal to the primary winding with a polarity that changes in response to a change of the input signal level. A latch circuit is arranged such that its set terminal is coupled to one end of the secondary winding of the transformer, and its reset terminal is coupled to the other end of the secondary winding of the transformer. A first switch is arranged between a common voltage node at which a common voltage occurs and the set terminal. When the output of the latch circuit is high, the first switch is turned on. A second switch is arranged between the common voltage node and the reset terminal. When the output of the latch circuit is low, the second switch is turned on.

A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

A signal processing circuit includes a signal path for outputting a first signal included in an input signal from a first output terminal to another signal processor; branch paths one of which extends from a top position located at a position on the signal path and the others which extend from associated branch positions that divide the signal path starting from the top position to the first output terminal into segments in each of which a first amount of delay obtained by equally dividing an amount of delay caused by the signal path and that is added to the first signal; a switch connected to each of the branch paths and switches whether to allow a second signal other than the first signal included in the input signal to pass through the connected branch paths; a variable gain amplifier connected to each of the switches and amplifies the second signal.

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

A clock monitor circuit detects departures from expected values for clock period, clock high time duration, or clock low time duration. A delay line of the clock monitor circuit is composed of delay portions of delay cells. Each delay cell also has a comparator portion with logic to compare aspects of the monitored clock signal to corresponding expected values, and to output a failure detection signal indicating whether the expected values are met. Expected values may be read from a fuse set. The delay of the delay line may be programmatically adjusted. The clock monitor circuit may be combined with a circuit that detects narrow glitches in the monitored clock signal. Devices and systems with one or more monitored clock signals, and methods of clock signal monitoring, are also described.

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.