A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

A driver circuit for low voltage differential signaling, LVDS, includes a phase alignment circuit including an input configured to receive an input signal, a first output configured to provide an internal signal as a function of the input signal, and a second output configured to provide an inverted internal signal, which is the inverted signal of the internal signal, and an output driver circuit coupled to the phase alignment circuit, the output driver circuit including a first input configured to receive the internal signal, a second input configured to receive the inverted internal signal, a first output configured to provide an output signal as a function of the internal signal and a second output configured to provide an inverted output signal which is the inverted signal of the output signal. Therein the phase alignment circuit is configured to provide the inverted internal signal with its phase being aligned to a phase of the internal signal.

Apparatus and associated methods relate to a low-noise wideband active phase shifter. The low-noise wideband active phase shifter includes first and second transconductance cells, a fixed LC series network and a tunable LC series network configured to form an all-pass lattice network. The first and second transconductance cells, each include a transistor, a feedback network, and a transistor biasing network. The transistor has an input terminal and an output terminal. The negative feedback network electrically couples the input and output terminals of the transistor. The biasing network provides input and output biasing of the transistor. The fixed LC series network connects between the first and the second transconductance cells. The tunable LC series network connects between the first and the second transconductance cells.

Provided is a phase self-correction circuit, including a trigger signal operation module and a signal phase correction module. The trigger signal operation module and the signal phase correction module are both composed of a plurality of discrete components. The trigger signal operation module is configured to perform a logical operation on an input phase standard reference signal and actual transmission signal, to obtain a target trigger signal for triggering the signal phase correction module; and the signal phase correction module is configured to output, based on trigger modes of the target trigger signal and the actual transmission signal, a self-correction transmission signal with the same waveform as that of the phase standard reference signal, to realize phase self-correction on the actual transmission signal.

A phase-shifted sampling module for sampling a signal is described. The phase-shifted sampling module includes a primary sampler module, an ADC module, and an equalization module. The primary sampler module includes an analog signal input, a first signal path, and a second signal path. The equalization module includes a primary sampler equalizer sub-module. The primary sampler equalizer sub-module is configured to compensate low-frequency mismatches between the first signal path and the second signal path. Further, a method for determining filter coefficients of an equalization module of a phase-shifted sampling module is described.

A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.

A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.