An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

A microcontroller is coupled to a detection circuit which generates a detection signal. The microcontroller includes a processing circuit and an input-output circuit. The processing circuit generates an output signal according to the detection signal. In response to the output signal being at a specific level, the processing circuit enables a reset signal. The input-output circuit includes a latch circuit and a counter circuit. The latch circuit latches the output signal to generate a latched signal. The counter circuit starts adjusting the count value in response to the reset signal being enabled. The counter circuit changes the level of the latched signal in response to the count value being equal to a predetermined value.

A microcontroller is coupled to a detection circuit which generates a detection signal. The microcontroller includes a processing circuit and an input-output circuit. The processing circuit generates an output signal according to the detection signal. In response to the output signal being at a specific level, the processing circuit enables a reset signal. The input-output circuit includes a latch circuit and a counter circuit. The latch circuit latches the output signal to generate a latched signal. The counter circuit starts adjusting the count value in response to the reset signal being enabled. The counter circuit changes the level of the latched signal in response to the count value being equal to a predetermined value.

A digital micromirror device includes a plurality of micromirror cells on a semiconductor die. Each respective cell includes a memory circuit and an electrode selection circuit. At least some of the micromirror cells include a micromirror and each respective memory circuit controls a micromirror tilt angle. For a given memory circuit controlled to a first tilt angle, a measurement circuit measures a first value indicative of a capacitance between a first electrode and the micromirror and measures a second value indicative of a capacitance on the second electrode. For a second micromirror tilt angle, the measurement circuit measures a third value indicative of a capacitance between the first electrode and the micromirror and measures a fourth value indicative of a capacitance on the second electrode. The measurement circuit generates a signal indicative of whether the micromirror is stuck at a particular angle or missing.

A digital micromirror device includes a plurality of micromirror cells on a semiconductor die. Each respective cell includes a memory circuit and an electrode selection circuit. At least some of the micromirror cells include a micromirror and each respective memory circuit controls a micromirror tilt angle. For a given memory circuit controlled to a first tilt angle, a measurement circuit measures a first value indicative of a capacitance between a first electrode and the micromirror and measures a second value indicative of a capacitance on the second electrode. For a second micromirror tilt angle, the measurement circuit measures a third value indicative of a capacitance between the first electrode and the micromirror and measures a fourth value indicative of a capacitance on the second electrode. The measurement circuit generates a signal indicative of whether the micromirror is stuck at a particular angle or missing.

Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.

Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.

An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

A microcontroller is coupled to a detection circuit which generates a detection signal. The microcontroller includes a processing circuit and an input-output circuit. The processing circuit generates an output signal according to the detection signal. In response to the output signal being at a specific level, the processing circuit enables a reset signal. The input-output circuit includes a latch circuit and a counter circuit. The latch circuit latches the output signal to generate a latched signal. The counter circuit starts adjusting the count value in response to the reset signal being enabled. The counter circuit changes the level of the latched signal in response to the count value being equal to a predetermined value.