The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

A circuit, for generating ultrahigh-precision digital pulse signals comprises: a pulse edge control circuit used for delaying a signal on an input pin and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin arrives.

A control system for a laser scanning projector includes a mirror controller generating horizontal and vertical mirror synchronization signals for an oscillating mirror apparatus based upon a mirror clock signal, and laser modulation circuitry. The laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of a received laser clock signal, and generates control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry generates the laser clock signal and sends the laser clock signal to the laser modulation circuitry, receives the horizontal and vertical mirror synchronization signals from the mirror controller, receives the horizontal and vertical laser synchronization signals from the laser modulation circuitry, and modifies the laser clock signal so as to achieve alignment between the horizontal and vertical mirror synchronization signals and the horizontal and vertical laser synchronization signals.

A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2.sup.n−1 times.

A battery monitoring system includes a battery monitoring ECU and battery monitoring devices which are sequentially connected in a connection configuration. The battery monitoring ECU includes a clock generator that generates a first clock signal. Each battery monitoring device includes a second clock generator that generates a second clock signal, a controller that causes a frequency correction block to correct a frequency of the second clock signal in line with the first clock signal and causes the battery monitor to monitor a battery cell using the second clock signal that has been corrected, and a switch that, according to an instruction of the battery monitoring ECU, switches a circuit configuration to a state in which a signal received from a preceding device is transmitted to a succeeding device in the connection configuration.

A battery monitoring system includes a battery monitoring ECU and battery monitoring devices which are sequentially connected in a connection configuration. The battery monitoring ECU includes a clock generator that generates a first clock signal. Each battery monitoring device includes a second clock generator that generates a second clock signal, a controller that causes a frequency correction block to correct a frequency of the second clock signal in line with the first clock signal and causes the battery monitor to monitor a battery cell using the second clock signal that has been corrected, and a switch that, according to an instruction of the battery monitoring ECU, switches a circuit configuration to a state in which a signal received from a preceding device is transmitted to a succeeding device in the connection configuration.

A control system includes a mirror controller generating horizontal and vertical mirror synchronization signals for a mirror based upon a mirror clock signal. Laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of first and second laser clock signals and generates control signals for a laser that emits a laser beam that impinges on the mirror. First synchronization circuitry receives the horizontal mirror synchronization signal and the horizontal laser synchronization signal, and modifies generation of the first laser clock signal to achieve alignment between the horizontal mirror synchronization signal and horizontal laser synchronization signal. Second synchronization circuitry receives the vertical mirror synchronization signal and the vertical laser synchronization signal, and modifies generation of the second laser clock signal to achieve alignment between the vertical mirror synchronization signal and vertical laser synchronization signal.

An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.