A solid state relay and a method for controlling a signal path between an AC-signal output and a load in a power amplifier assembly are disclosed. The relay comprises a first and a second MOSFET having a common gate junction, a common source junction and wherein and wherein a drain terminal of a first MOSFET and a drain terminal of a second MOSFET form relay terminals. The solid state relay further comprises a control circuit comprising a positive side comprising a first controlled current generator configured to provide a first control current to the gate junction, and a negative side comprising a current mirror circuit configured to sink a second current from the source junction. Hereby, a generic solid state speaker relay has been disclosed. The relay performs up to the most stringent demands regarding pop/click on high quality products. It can be used to ground wire break, hot wire break and BTL (Bridge Tied Load) break. The design is rather tolerable to different MOSFETs and very competitive in quality and price.

A load control device for controlling power delivered from an AC power source to an electrical load may have a closed-loop gate drive circuit for controlling a semiconductor switch of a controllably conductive device. The controllably conductive device may be coupled in series between the source and the load. The gate drive circuit may generate a target signal in response to a control circuit. The gate drive circuit may shape the target signal over a period of time and may increase the target signal to a predetermined level after the period of time. The gate drive circuit may receive a feedback signal that indicates a magnitude of a load current conducted through the semiconductor switch. The gate drive circuit may generate a gate control signal in response to the target signal and the feedback signal, and render the semiconductor switch conductive and non-conductive in response to the gate control signal.

In an embodiment, a phase change switch device is provided. The phase change switch includes a phase change material, a set of heaters arranged to heat the phase change material and a power source. A switch arrangement including a plurality of switches is provided, which is configured to selectively provide electrical power from the power source to the set of the heaters.

Circuitry and techniques for providing a bidirectional switch in devices for overcurrent protection and voltage protection are disclosed herein. In one embodiment, a circuit may include a first reverse-blocking insulating gate bipolar transistor (IGBT), having a first gate terminal, first collector terminal and a first emitter terminal. The circuit may include a second reverse-blocking IGBT, having a second gate terminal, a second collector terminal, electrically coupled to the first emitter terminal, and a second emitter terminal, electrically coupled to the first collector terminal. As such the first IGBT and the second IGBT may define a first current path, extending from the first collector to the second emitter; and a switch control circuit, coupled to send a control signal to at least one of: the first gate terminal and the second gate terminal, during an overcurrent event.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

Apparatus for performing substrate voltage management is provided herein and comprises an active substrate voltage management circuit configured to be coupled to a substrate of a bidirectional gallium nitride high electron mobility transistor comprising a first source and a second source. The active substrate voltage management circuit comprises a first circuit that is connected to the first source and a second circuit that is connected to a second source such that when the bidirectional gallium nitride high electron mobility transistor is operational one of the first circuit or the second circuit connects one of the first source to the substrate or the second source to the substrate, respectively, to control a bias voltage applied to the substrate.

The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

The present description concerns a method of controlling a bidirectional switch (200), including: first (210 1) and (210 2) field-effect transistors electrically in series between first (262 1) and second (262 2) terminals of the bidirectional switch; third (614) and fourth (612) field-effect transistors electrically in series between said first and second terminals of the bidirectional switch, a first connection node (252) in series with the first and second transistors being common with a second connection node (616) in series with the third and fourth transistors, including steps of: receiving a voltage (V200) between the terminals of the bidirectional switch; detecting, from the received voltage, a first sign of said voltage; at least while the first sign is being detected, coupling the first terminal to said first node (252), potentials of control terminals of the first, second, third, and fourth transistors being referenced to the potential (REF) of the first and second nodes having common sources of the first, second, third, and fourth transistors connected thereto.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.