A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.

In accordance with an embodiment, a method of controlling a switch driver includes energizing a first inductor in a first direction with a first energy; transferring the first energy from the first inductor to a second inductor, wherein the second inductor is coupled between a second switch-driving terminal of the switch driver and a second internal node, and the second inductor is magnetically coupled to the first inductor; asserting a first turn-on signal at the second switch-driving terminal using the transferred first energy; energizing the first inductor in a second direction opposite the first direction with a second energy after asserting the first turn-on signal at the second switch-driving terminal; transferring the second energy from the first inductor to the second inductor; and asserting a first turn-off signal at the second switch-driving terminal using the transferred second energy.

A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.

The present disclosure provides a motor drive device. The motor drive device includes a current detection unit, a control unit and a determination unit. The current detection unit detects a current flowing through a motor coil. The control unit executes a slow attenuation mode that attenuates the current after an end of a power supply mode. The determination unit determines whether the current at a second time point while a predetermined time has elapsed from a first time point when the power supply mode is switched to a slow decay mode is below a limit value. When the determination unit determines that the current does not fall below the limit value, the control unit is configured to switch from the slow attenuation mode to a fast attenuation mode at the second time point.

A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.

An electric power conversion circuit includes: first through fourth port terminals; a first diode having an anode connected to the first port terminal; a second diode having a cathode connected to the second port terminal; a third diode having a cathode connected to the first port terminal; a fourth diode having an anode connected to the second port terminal; first through fourth switches that are bridge-connected between a cathode of the first diode and an anode of the second diode; fifth through eighth switches that are bridge-connected between an anode of the third diode and a cathode of the fourth diode; a first bootstrap circuit that is connected to control terminals of the first through fourth switches; and a second bootstrap circuit that is connected to control terminals of the fifth through eighth switches.

A switching system can include a main switching device configured to switch a voltage, a gate driver having an output coupled to a drive terminal of the main switching device and configured to deliver a drive signal to the main switching device, and a clamp circuit. The clamp circuit can be coupled to the drive terminal of the main switching device. The clamp circuit can include a logic gate configured to drive a clamp switching device coupled to and configured to clamp a voltage at the drive terminal of the main switching device. A drive signal of the clamp switching device can be substantially complementary to the main switching device drive signal. The logic gate can provide at least a portion of a delay between switching transitions of the main switching device and switching transitions of the clamp switching device.

A full-wave rectifier is disclosed. In one embodiment the full-wave rectifier includes two input paths configured to receive an alternating input voltage, two output paths configured to provide a direct output voltage, and four switched-mode rectifying paths that are connected between each of the input paths and each of the output paths, wherein the switched mode rectifying paths are configured to connect a first input path to a first output path and a second input path to a second output path during a first half wave of the input voltage, and to connect the first input path to the second output path and the second input path to the first output path during a second half wave of the input voltage, and wherein the switched-mode rectifying paths include cascode circuits.

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.