A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The first switch is coupled between a node and a reference voltage. The second switch is coupled between the control terminal of the first transistor and the node. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the node and the output terminal of the inverter circuit.

An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.

A solid state relay and a method for controlling a signal path between an AC-signal output and a load in a power amplifier assembly are disclosed. The relay comprises a first and a second MOSFET having a common gate junction, a common source junction and wherein and wherein a drain terminal of a first MOSFET and a drain terminal of a second MOSFET form relay terminals. The solid state relay further comprises a control circuit comprising a positive side comprising a first controlled current generator configured to provide a first control current to the gate junction, and a negative side comprising a current mirror circuit configured to sink a second current from the source junction. Hereby, a generic solid state speaker relay has been disclosed. The relay performs up to the most stringent demands regarding pop/click on high quality products. It can be used to ground wire break, hot wire break and BTL (Bridge Tied Load) break. The design is rather tolerable to different MOSFETs and very competitive in quality and price.

A differential switch circuit includes: a first transistor having a first terminal coupled with a first input terminal, a second terminal coupled with a first output terminal, and a control terminal coupled with a switch signal receiving terminal; a second transistor having a first terminal coupled with a second input terminal, a second terminal coupled with a second output terminal, and a control terminal coupled with the switch signal receiving terminal; a central switch element positioned between the control terminals of the first and second transistors; and a switch element control circuit for controlling the central switch element based on a switch signal. When the switch signal turns on the first and second transistors, the switch element control circuit turns off the central switch element, and when the switch signal turns off the first and second transistors, the switch element control circuit turns on the central switch element.

A semiconductor switch control device includes a first FET and a second FET arranged adjacent to each other, in which source terminals are connected in series. A drain terminal of the first FET is connected to a high voltage battery, and a drain terminal of the second FET is connected to a high voltage load. A controller determines a temperature state of a minus-side main relay including the second FET based on a forward voltage of a body diode of the first FET.

According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.

A charge sensitive amplifier circuit for sensor frontend comprises an input node to be connected to a sensor to receive an input charge, and an output node to be connected to a charge conversion circuit. The charge sensitive amplifier circuit comprises a first transfer switch located between the input node and the output node to transfer the input charge to the output node. The charge sensitive amplifier circuit further comprises a second transfer switch located in parallel to the first transfer switch between the input node and the output node to transfer the input charge to the output node.

A switch control circuit a multiplexer switch circuit and a control method for a multiplexer switch control circuit are provided. The switch control circuit comprises a first control switch, a first capacitor and a field-effect transistor switch. When the first control switch is switched off, a charging voltage released by the first capacitor can control the switching-on of the field-effect transistor switch. At this moment, since the first control switch is switched off, and a power source signal cannot reach a gate electrode of the field-effect transistor switch, power source noise cannot be coupled to a line where source and drain electrodes of the field-effect transistor switch are located. Thus, in a discharge stage of the first capacitor, a discharge voltage can serve as a control signal to control the switching-on of the field-effect transistor switch.

A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

A level conversion circuit includes a first pin, a second pin, a target pin, a core module and a switch. A first terminal of the switch is connected to the first pin, a second terminal of the switch is connected to the second pin, and the core module is connected to the target pin, the second pin and a control terminal of the switch respectively. The core module is configured to: when a voltage connected to the target pin is at a first reference high level, control the switch to turn on to transmit a signal with a specified voltage amplitude, and pull the first pin to the first reference high level and the second pin to a second reference high level based on the first reference high level; where the first reference high level is higher than the second reference high level.