A comb signal generator that includes at least two signal sources that each provide a signal, wherein the signals provided by the at least two signal sources are shaped similarly. The com signal generator also has a combining circuit connected with the at least two signal sources, wherein the combining circuit is configured to combine the signals provided by the at least two signal sources, thereby generating a combined signal. Further, the com signal generator includes a clipping circuit connected with the combining circuit, wherein the clipping circuit is configured to receive and process the combined signal, thereby generating a comb signal. Further, a method of providing a phase and amplitude reference is described.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In certain configurations, a negative voltage generator includes a charge pump controllable by a clock signal and configured to provide a negative voltage at an output node, an oscillator configured to activate based on an enable signal and to provide the clock signal to the charge pump, a comparator configured to generate the enable signal based on comparing a feedback voltage with a reference value, a voltage divider electrically connected between a positive voltage node and the output node and configured to generate the feedback voltage at a feedback node, and a start-up capacitor electrically connected between the positive voltage node and the feedback node and configured to control a settling time of the feedback voltage.

Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In certain configurations, a negative voltage generator includes a charge pump controllable by a clock signal and configured to provide a negative voltage at an output node, an oscillator configured to activate based on an enable signal and to provide the clock signal to the charge pump, a comparator configured to generate the enable signal based on comparing a feedback voltage with a reference value, a voltage divider electrically connected between a positive voltage node and the output node and configured to generate the feedback voltage at a feedback node, and a start-up capacitor electrically connected between the positive voltage node and the feedback node and configured to control a settling time of the feedback voltage.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

An electric fence energizer including an IPC (isolated power coupling) power transmitter and an IPC power receiver adapted to receive power from the IPC power transmitter and supply power to the energizer. A pulse shaping circuit between an energy source and output transformer of the energizer may include a series inductance of between 2 μH to 20 μH and a parallel capacitance of between 3μF to 30 μF. The energizer output transformer may comprise a primary winding consisting of less than 15 turns and a secondary winding of between 5 and 50 times the number of turns of the primary winding. The energizer may produce a pulse having a duration of between 20 μs and 60 μs and a peak amplitude greater than 5 kV into 300 Ω.

An electric fence energizer including an IPC (isolated power coupling) power transmitter and an IPC power receiver adapted to receive power from the IPC power transmitter and supply power to the energizer. A pulse shaping circuit between an energy source and output transformer of the energizer may include a series inductance of between 2 μH to 20 μH and a parallel capacitance of between 3μF to 30 μF. The energizer output transformer may comprise a primary winding consisting of less than 15 turns and a secondary winding of between 5 and 50 times the number of turns of the primary winding. The energizer may produce a pulse having a duration of between 20 μs and 60 μs and a peak amplitude greater than 5 kV into 300 Ω.

A semiconductor apparatus includes a control circuit and a level shifter. The control circuit is configured to output a power control signal for activating a data input/output circuit operated by a first voltage when the first voltage is higher than a first set voltage and a second voltage is higher a second set voltage. The level shifter configured to receive the power control signal and lower operating voltages of devices including a plurality of transistors with a thin gate insulating layer based on the power control signal.