An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

A microwave generator includes a power supply, an output circuit, a feedback oscillator, a pulse controller, a signal combination circuit and a semiconductor amplifier. The power supply converts input voltage and input current into output voltage and output current. The output circuit generates a microwave signal to an output terminal of the microwave generator and a feedback signal according to the microwave signal. The feedback oscillator generates an oscillation signal according to the feedback signal. According to a reference signal, the pulse controller generates a pulse signal. According to the oscillation signal and pulse signal, the signal combination circuit generates a control signal. The semiconductor amplifier generates and adjusts an amplified signal according to the control signal. The output circuit generates the microwave signal according to the amplified signal. The output current is adjusted according to the amplified signal. Consequently, the input current and the input voltage are in phase.

The present disclosure provides a controller for controlling a GaN-based semiconductor device. The controller is configured to receive a current sensing signal V.sub.CS which is indicative of a drain-to-source current of the GaN-based semiconductor device and generate a control driving signal V.sub.DRV to the GaN-based semiconductor device such that a gate-to-source voltage V.sub.GS applied to the GaN-based semiconductor device for switching on the GaN-based semiconductor device is stabilized to a voltage value equal to a reference voltage V.sub.ref over an on-time duration. Impact of the change in the voltage drop across the current sensing resistor to the operation of the GaN-based semiconductor device is eliminated.

A temperature delay device includes a first thermal sensor, a second thermal sensor, an inverter, and a latch circuit. The first thermal sensor is configured to measure a first temperature of a chip to output a first input signal. The second thermal sensor is configured to measure a second temperature of the chip to output a second input signal. The inverter is coupled to the first thermal sensor, and is configured to reverse the first input signal so as to output a third input signal. The latch circuit is coupled to the inverter and the second thermal sensor, and is configured to output an output signal according to the second input signal and the third input signal. The first temperature is different from the second temperature.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. The first transistor is controlled by a enable signal. The second transistor is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit generates the second control signal according to the first control signal and the enable signal.

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

The disclosure provides a charging device, which includes an input terminal configured to receive an input voltage; an output terminal configured to connect a target load so as to charge the target load; a control terminal, configured to receive a control voltage; a junction field-effect transistor and a control circuit. The junction field-effect transistor includes at least: a drain, electrically connected to the input terminal so as to receive the input voltage; a source, electrically connected to the output terminal so as to output an output voltage and an output current; and a gate, electrically connected to the control terminal. The control circuit is electrically connected to the control terminal, and configured to change the control voltage based on a change in a load voltage so as to change a pinch-off voltage of the JFET by controlling a bias voltage on the gate, thereby controlling the output current.

An active gate driver suitable for activating an electronic switch of an electric motor. The active gate driver includes a pull up branch, a pull down branch and a current and voltage feedback from an output of the active gate driver to at least one input of the active gate driver, wherein the current and voltage feedback is common to both the pull up branch and the pull down branch.