A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.

An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a course tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

A signal generation circuit includes: a clock circuit configured to receive a flag signal and generate a clock signal; a control circuit configured to generate a control circuit; and a generation circuit connected to both the clock circuit and control circuit and configured to receive the clock signal, the control signal, and the flag signal and generate a target signal, wherein when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal is maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level; and the generation circuit is further configured to determine the target duration according to the clock signal and control signal.

One example includes an Ising machine system. The system includes a plurality of ring oscillators that are each configured to propagate an oscillation signal. Each of the ring oscillators can be cross-coupled with at least one other of the ring oscillators via a respective one of the oscillation signals to provide a respective phase coupling between the respective cross-coupled ring oscillators. The system also includes an Ising machine controller configured to generate control signals corresponding to parameters of an Ising problem and including a plurality of delay selection signals. The Ising machine controller can provide at least one of the delay selection signals to each of the ring oscillators. The delay selection signal can be configured to set a variable propagation delay of the ring oscillator to control the relative phase coupling of each of the ring oscillators to each of the at least one other of the ring oscillators.

Apparatus and methods for radio frequency (RF) switch control are provided. In certain embodiments, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a negative charge pump voltage and a first output that provides a first switch control signal, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor and controlled by a first switch enable signal.

A semiconductor integrated circuit includes a first oscillator configured to generate a first signal with a first frequency based on a control signal and output the first signal to a path. The semiconductor integrated circuit includes a control signal generation circuit operatively coupled to the first oscillator via the path, and configured to receive the first signal from the first oscillator via the path and generate the control signal. The semiconductor integrated circuit includes a second oscillator configured to generate a second signal with a second frequency based on the control signal and output the second signal to an output terminal outside the path.

The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.

In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.