A duty cycle correction circuit includes a detection block suitable for detecting a duty cycle of a first clock in response to the first clock and a second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a detection result of the detection block.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.

A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.

In some examples, a circuit comprises a first switch adapted to be coupled to a direct current (DC) power source, a second switch coupled to the first switch and adapted to be coupled to the DC power source, and a resistor coupled to the first and second switches. The circuit comprises a transformer having a primary side and a secondary side, the primary side coupled to the first and second switches, the secondary side adapted to be coupled to a load. The circuit comprises a third switch coupled between the resistor and the primary side of the transformer, and a capacitor coupled to the second switch.

In some examples, a circuit comprises a first switch adapted to be coupled to a direct current (DC) power source, a second switch coupled to the first switch and adapted to be coupled to the DC power source, and a resistor coupled to the first and second switches. The circuit comprises a transformer having a primary side and a secondary side, the primary side coupled to the first and second switches, the secondary side adapted to be coupled to a load. The circuit comprises a third switch coupled between the resistor and the primary side of the transformer, and a capacitor coupled to the second switch.

A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.