Common-mode transient immunity circuit and modulation-demodulation circuit, common-mode transient immunity circuit is applied to connecting with modulation circuit or demodulation circuit, comprising first isolation circuit, common-mode bias circuit, reference circuit and comparison circuit. Common-mode bias circuit provides common-mode bias voltage for first isolation circuit; first isolation circuit transmits common-mode bias voltage to comparison circuit; reference circuit provides reference voltage for comparison circuit; comparison circuit compares common-mode bias voltage with reference voltage, when common-mode bias voltage is larger than reference voltage, comparison circuit outputs enable signal to modulation circuit or demodulation circuit, and modulation circuit is driven to stop outputting modulation signal or demodulation circuit is driven to stop receiving modulation signal. According to invention, when common-mode transient occurs, enable signal is output to drive modulation circuit or demodulation circuit to stop working, so that influence of common-mode transient on output signal is avoided.

A circuit for compensation of baseline voltage wander operating at an input of an isolator is disclosed. The circuit can compensate electronically the frequency response of an isolation circuit (e.g., a transformer) by increasing the pass band in the low frequency region in order to minimize the baseline wander caused by low inductance windings. The compensation circuit can be used to inject a current ramp proportional to the amplitude and the duration of the pulse and inversely proportional to the open circuit inductance of the isolation circuit.

A circuit for compensation of baseline voltage wander operating at an input of an isolator is disclosed. The circuit can compensate electronically the frequency response of an isolation circuit (e.g., a transformer) by increasing the pass band in the low frequency region in order to minimize the baseline wander caused by low inductance windings. The compensation circuit can be used to inject a current ramp proportional to the amplitude and the duration of the pulse and inversely proportional to the open circuit inductance of the isolation circuit.

A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control signal. When there is a positive glitch in the output signal and a voltage level of the glitch amplifier output signal is less than a first threshold voltage, the pulse generator deactivates the control signal, which turns off the transistor. When there is a negative glitch in the output signal and the voltage level of the glitch amplifier output signal is greater than a second threshold voltage, the pulse generator activates the control signal, which turns on the transistor and provides a compensating current surge to reduce a voltage droop in the output signal.

A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control signal. When there is a positive glitch in the output signal and a voltage level of the glitch amplifier output signal is less than a first threshold voltage, the pulse generator deactivates the control signal, which turns off the transistor. When there is a negative glitch in the output signal and the voltage level of the glitch amplifier output signal is greater than a second threshold voltage, the pulse generator activates the control signal, which turns on the transistor and provides a compensating current surge to reduce a voltage droop in the output signal.

A comparator circuit having an offset voltage includes a first input circuit, a second input circuit and a control circuit. The first input circuit includes a first input terminal receiving a first input signal. The second input circuit includes a second input terminal receiving a second input signal. The control circuit is coupled to a first intermediate terminal and a second intermediate terminal and resets a voltage at the first intermediate terminal and a voltage at the second intermediate terminal according to an offset cancellation voltage. The first intermediate terminal is coupled between the first input terminal and a first output terminal of the comparator circuit, the second intermediate terminal is coupled between the second input terminal and a second output terminal of the comparator circuit, and the first intermediate terminal and the second intermediate terminal are symmetric terminals in the comparator circuit.

A comparator circuit having an offset voltage includes a first input circuit, a second input circuit and a control circuit. The first input circuit includes a first input terminal receiving a first input signal. The second input circuit includes a second input terminal receiving a second input signal. The control circuit is coupled to a first intermediate terminal and a second intermediate terminal and resets a voltage at the first intermediate terminal and a voltage at the second intermediate terminal according to an offset cancellation voltage. The first intermediate terminal is coupled between the first input terminal and a first output terminal of the comparator circuit, the second intermediate terminal is coupled between the second input terminal and a second output terminal of the comparator circuit, and the first intermediate terminal and the second intermediate terminal are symmetric terminals in the comparator circuit.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

According to an embodiment, a semiconductor device includes a differential input circuit suitable for receiving first and second input signals respectively inputted to first and second input transistors, and outputting an output signal; a comparison circuit suitable for generating a first judge signal by comparing the output signal with a first comparison voltage, and generating a second judge signal by comparing the output signal with a second comparison voltage, in a calibration mode; an offset control circuit suitable for adjusting coarse codes and fine codes, according to the first and second judge signals; and an offset adjusting circuit suitable for adjusting a drivability of each of the first and second input transistors by a first strength, according to the coarse codes, and adjusting the drivability of each of the first and second input transistors by a second strength smaller than the first strength, according to the fine codes.