A control arrangement is disclosed for providing a plurality of phase-coherent oscillating signals. It comprises a reference clock signal arrangement for providing a high-frequency reference clock signal and a plurality of modules each comprising a plurality of channels for providing the plurality of phase-coherent oscillating signals.

A control arrangement is disclosed for providing a plurality of phase-coherent oscillating signals. It comprises a reference clock signal arrangement for providing a high-frequency reference clock signal and a plurality of modules each comprising a plurality of channels for providing the plurality of phase-coherent oscillating signals.

A data network has at least three line branches connected via a common star node to distribute message signals from one of the line branches onto the other line branches, wherein connected to at least one of the line branches is at least one bus-user device is configured to generate in a corresponding transmit mode by a corresponding transmit unit at least one of the message signals, wherein in the corresponding bus-user device, the transmit unit has a current source circuit which, in generating the message signal (16), is configured to inject an electric current into electrical lines of the line branch to which the bus-user device is connected, and via the current source circuit the lines are connected to an internal impedance value of the current source circuit that in transmit mode is constantly greater than 10 times the value of the characteristic impedance, for example greater than 500 Ohms.

A data network has at least three line branches connected via a common star node to distribute message signals from one of the line branches onto the other line branches, wherein connected to at least one of the line branches is at least one bus-user device is configured to generate in a corresponding transmit mode by a corresponding transmit unit at least one of the message signals, wherein in the corresponding bus-user device, the transmit unit has a current source circuit which, in generating the message signal (16), is configured to inject an electric current into electrical lines of the line branch to which the bus-user device is connected, and via the current source circuit the lines are connected to an internal impedance value of the current source circuit that in transmit mode is constantly greater than 10 times the value of the characteristic impedance, for example greater than 500 Ohms.

A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals. The latches receive two delayed input signals provided by the delay circuits based upon the feedback signals.

A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals. The latches receive two delayed input signals provided by the delay circuits based upon the feedback signals.

In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.

A transformer includes a primary winding and a secondary winding. A transmitting circuit is coupled to a primary winding of a transformer and supplies a current signal to the primary winding with a polarity that changes in response to a change of the input signal level. A latch circuit is arranged such that its set terminal is coupled to one end of the secondary winding of the transformer, and its reset terminal is coupled to the other end of the secondary winding of the transformer. A first switch is arranged between a common voltage node at which a common voltage occurs and the set terminal. When the output of the latch circuit is high, the first switch is turned on. A second switch is arranged between the common voltage node and the reset terminal. When the output of the latch circuit is low, the second switch is turned on.