A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Embodiments of the present disclosure provide a driving circuit and a lamp comprising the same. The driving circuit comprises inputs connected to a mains supply; outputs connected to an LED load; an output capacitor connected in parallel with the LED load; an LED driving current source connected to the outputs, and configured to convert the mains supply at the inputs to current at the outputs in an illumination mode, such that the current flows through the LED load and charges the output capacitor; and a control circuit configured to receive a standby signal to enable a standby mode, and to control the mains supply to linearly charge the output capacitor in the standby mode, such that an output voltage at the output can be lower than a turn-on voltage of the LED load and is higher than a preset lowest voltage. With the driving circuit, it is advantageous to reduce the delay from the standby mode to a minimum light emitting level, and meanwhile a lower power loss can be realized by linearly charging the output capacitor through the mains supply.

A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value.

Disclosed embodiments relate to sensing states and changes of states of a signal and sensors for the same, including but not limited to, autonomous sensors. Such sensor may include an analog signal threshold detection circuit, a state detection circuit, and a measurement circuit. The analog signal threshold detection circuit may be configured to alternately assert and de-assert a threshold detected indication in response to an input signal and a state thereof. The state detection circuit may be configured to generate a signal state indication about a state of the input signal. The measurement circuit may be configured to generate a measurement in response to assertions of the threshold detected indication and the signal state indication, such as a count, a slew rate, or a frequency. In some embodiments, disclosed sensors may have programmable thresholds for sensing the signal states and changes therein.

A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison a reference voltage to the magnitude of signals received via a communication link that encode a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a indicating the presence of data on the communication link. Once the is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.

A comparator circuit includes: a comparator comprising: a first input terminal receiving an input voltage; a second input terminal receiving a reference voltage; an output terminal outputting an output signal according to a result of a comparison between the input voltage and the reference voltage; and a power supply terminal receiving an operating voltage; and a mode controller applying a first operating voltage and a first reference voltage to the second input terminal and the power supply terminal of the comparator for a predetermined delay time in response to a supply of power being initiated from a power supply, and applying a second operating voltage and a second reference voltage to the second input terminal and the power supply terminal of the comparator in response to the delay time elapsing, wherein the first operating voltage is higher than a ground voltage and is lower than the second operating voltage.

A comparator circuit includes: a comparator comprising: a first input terminal receiving an input voltage; a second input terminal receiving a reference voltage; an output terminal outputting an output signal according to a result of a comparison between the input voltage and the reference voltage; and a power supply terminal receiving an operating voltage; and a mode controller applying a first operating voltage and a first reference voltage to the second input terminal and the power supply terminal of the comparator for a predetermined delay time in response to a supply of power being initiated from a power supply, and applying a second operating voltage and a second reference voltage to the second input terminal and the power supply terminal of the comparator in response to the delay time elapsing, wherein the first operating voltage is higher than a ground voltage and is lower than the second operating voltage.

A method of reducing bit error rate in a PAM4 clock data recovery circuit is described. The method includes determining a first target value of a slicing level, sweeping down from an upper voltage threshold to determine a first reference voltage value, and detecting a first filtered analog output associated with the first reference voltage value. The method also includes sweeping up from a lower voltage threshold to determine a second reference voltage value and detecting a second filtered analog output associated with the second reference voltage value. The first reference voltage value and the second reference voltage value are averaged to determine a calculated threshold value.

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.