A tamper-resistant actuator includes a valid input, configured to deliver an input electrical current through a circuit. A high-pass filter is positioned within the circuit that degrades components of the input electrical current that are outside of a predefined current range. Components that are within the predefined current range define an output current. A transistor activates a switch when the output current from the high-pass filter is received by the transistor.

A tamper-resistant actuator includes a valid input, configured to deliver an input electrical current through a circuit. A high-pass filter is positioned within the circuit that degrades components of the input electrical current that are outside of a predefined current range. Components that are within the predefined current range define an output current. A transistor activates a switch when the output current from the high-pass filter is received by the transistor.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

An I2C wake-up circuit, method and electronic device are disclosed. The I2C wake-up circuit includes: a clock wake-up circuit, configured to send a clock wake-up signal to a clock circuit in response to detecting a start signal on a serial clock line SCL and a serial data line SDA; and a signal hold circuit, configured to hold the serial data line SDA in a state of not transmitting address information until a clock signal sent by the clock circuit that is wake-up is received. The present I2C wake-up solution can realize normal data reception through a simple hardware circuit without a specific address wake-up and maximize power saving by turning on the clock when there is access and turning off the clock when the access ends.

An I2C wake-up circuit, method and electronic device are disclosed. The I2C wake-up circuit includes: a clock wake-up circuit, configured to send a clock wake-up signal to a clock circuit in response to detecting a start signal on a serial clock line SCL and a serial data line SDA; and a signal hold circuit, configured to hold the serial data line SDA in a state of not transmitting address information until a clock signal sent by the clock circuit that is wake-up is received. The present I2C wake-up solution can realize normal data reception through a simple hardware circuit without a specific address wake-up and maximize power saving by turning on the clock when there is access and turning off the clock when the access ends.

An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

A compensation circuit configured for coupling to a voltage source and a reference circuit. The voltage source is configured for supplying a supply voltage to the compensation circuit and the reference circuit. The reference circuit includes a first circuit node and a reference output electrically coupled to the first circuit node for outputting a reference signal having a constant reference amplitude. The compensation circuit includes a transient converter for converting a first transient perturbation of the supply voltage into a first compensation electrical signal proportional to said first transient perturbation, and an adder coupled to the transient converter for adding the first compensation electrical signal to an electrical signal at the first circuit node with a first polarity opposite to a disturbance polarity of a disturbance of the electrical signal in response to the first transient perturbation.

A compensation circuit configured for coupling to a voltage source and a reference circuit. The voltage source is configured for supplying a supply voltage to the compensation circuit and the reference circuit. The reference circuit includes a first circuit node and a reference output electrically coupled to the first circuit node for outputting a reference signal having a constant reference amplitude. The compensation circuit includes a transient converter for converting a first transient perturbation of the supply voltage into a first compensation electrical signal proportional to said first transient perturbation, and an adder coupled to the transient converter for adding the first compensation electrical signal to an electrical signal at the first circuit node with a first polarity opposite to a disturbance polarity of a disturbance of the electrical signal in response to the first transient perturbation.

The invention relates to a detection apparatus (12) for detecting photons. The detection apparatus comprises a pile-up determining unit (15) for determining whether detection signal pulses being indicative of detected photons are caused by a pile-up event or by a non-pile-up event, wherein a detection values generating unit (16) generates detection values depending on the detection signal pulses and depending on the determination whether the respective detection signal pulse is caused by a pile-up event or by a non-pile-up event. In particular, the detection values generating unit can be adapted to reject the detection signal pulses caused by pile-up events while generating the detection values. This allows for an improved quality of the generated detection values.