A control arrangement is disclosed for providing a plurality of phase-coherent oscillating signals. It comprises a reference clock signal arrangement for providing a high-frequency reference clock signal and a plurality of modules each comprising a plurality of channels for providing the plurality of phase-coherent oscillating signals.

Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.

A trigger signal provided via a pulse-per-second input port of a network interface controller is detected. In response to the trigger signal, an internal hardware clock value of the network interface controller is recorded. The recorded internal hardware clock value is reported, wherein the reported internal hardware clock value is reported for use in determining a timing error of the network interface controller based at least in part on a comparison with a time value of another device that also received the trigger signal.

A trigger signal provided via a pulse-per-second input port of a network interface controller is detected. In response to the trigger signal, an internal hardware clock value of the network interface controller is recorded. The recorded internal hardware clock value is reported, wherein the reported internal hardware clock value is reported for use in determining a timing error of the network interface controller based at least in part on a comparison with a time value of another device that also received the trigger signal.

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

A delay circuit provides a programmable delay and includes an input selector circuit to select between a loop delay output signal and an input signal. A loop delay circuit provides a loop delay to the input signal and supplies the loop delay output signal. The input signal can be recirculated through the loop delay circuit to extend the range of the delay. The input selector circuit selects the feedback signal during recirculation. A variable delay circuit provides a variable delay to the loop delay output signal after the recirculation is complete and supplies a variable delay output signal. An output selector circuit selects the output of the output selector circuit during the recirculation and selects the variable delay output signal after the recirculation is complete to thereby provide a delayed signal with the delay based on the loop delay, the number of loops of recirculation, and the variable delay.

A delay circuit provides a programmable delay and includes an input selector circuit to select between a loop delay output signal and an input signal. A loop delay circuit provides a loop delay to the input signal and supplies the loop delay output signal. The input signal can be recirculated through the loop delay circuit to extend the range of the delay. The input selector circuit selects the feedback signal during recirculation. A variable delay circuit provides a variable delay to the loop delay output signal after the recirculation is complete and supplies a variable delay output signal. An output selector circuit selects the output of the output selector circuit during the recirculation and selects the variable delay output signal after the recirculation is complete to thereby provide a delayed signal with the delay based on the loop delay, the number of loops of recirculation, and the variable delay.