A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.

A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.

A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.

Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.

Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.

Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.

Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.

An oscillator circuit (100) comprises a first tank circuit (T1) comprising an inductive element (L) and a capacitive element (C) coupled in series between a first voltage rail (14) and a first drive node (12). A feedback stage (F) is coupled to a first tank output (13) of the first tank circuit (T1) and to the first drive node (12). The feedback stage (F) is arranged to generate, responsive to a first oscillating tank voltage present at the first tank output (13), a first oscillating drive signal at the first drive node (12) in-phase with a first oscillating tank current flowing in the inductive element (L) and the capacitive element (C), thereby causing the oscillator (100) to oscillate in a series resonance mode of the inductive element (L) and the capacitive element (C).

An oscillator circuit (100) comprises a first tank circuit (T1) comprising an inductive element (L) and a capacitive element (C) coupled in series between a first voltage rail (14) and a first drive node (12). A feedback stage (F) is coupled to a first tank output (13) of the first tank circuit (T1) and to the first drive node (12). The feedback stage (F) is arranged to generate, responsive to a first oscillating tank voltage present at the first tank output (13), a first oscillating drive signal at the first drive node (12) in-phase with a first oscillating tank current flowing in the inductive element (L) and the capacitive element (C), thereby causing the oscillator (100) to oscillate in a series resonance mode of the inductive element (L) and the capacitive element (C).

A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.