A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.

A clock transmission circuit includes a first buffer, a second buffer, and an inductor unit. The first buffer is configured to receive a first clock which is one of differential clocks, and to buffer and output the first clock to a first clock wiring. The second buffer is configured to receive a second clock which is the other of the differential clocks, and to buffer and output the second clock to a second clock wiring. The inductor unit is connected between a first node of the first clock wiring and a second node of the second clock wiring, and configured to include a center tap to which a common voltage is applied.

A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.

A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180 phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.

A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.