Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.

Apparatuses and methods of widespread equispatiated phase generation of a clock divided by a non-integer factor are described. One integrated circuit includes a clock divider and a phase generator. The clock divider receives a single-phase clock signal from a clock source and generates a divided clock signal. The phase generator receives the divided clock signal and the single-phase clock signal and generates multiple phase signals using the divided clock signal and the single-phase clock signal. The phase signals are equispatiated.

Provided is a data transmitter including a signal interval determination unit configured to receive a data input signal corresponding to data to be transmitted, determine time intervals between a synchronization signal and a plurality of data signals according to the data input signal, and output interval signals corresponding to the intervals; a trigger generation unit configured to trigger according to an output signal from the signal interval determination unit; and a signal generation unit configured to receive the trigger to generate the synchronization signal and the data signals.

An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

There is provided an electronic circuit including a timing signal generation unit for generating a timing signal; a data signal supply unit for synchronizing with the timing signal generated to supply a data signal; a data signal transmission circuit for transmitting the data signal supplied; a timing signal transmission circuit for transmitting the timing signal generated by a circuit having a substantially same delay time as the data signal transmission circuit; and a data holding unit for synchronizing with the timing signal transmitted to hold and output the data signal transmitted. Also, there are provided a solid state image capturing apparatus and a method of controlling the electronic circuit.

A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit, a signal generation circuit, and a duty cycle adjustment circuit. The duty cycle adjustment circuit is configured to generate a target voltage having a duty cycle that is equal to a target duty cycle, the control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the target voltage and the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the target voltage and the frequency control word, and the spread spectrum output signal corresponds to the frequency control word and a duty cycle of the spread spectrum output signal is the target duty cycle.

A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.