Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

A method and apparatus for determining a set of cascading clock cycles, the method comprising inputting a set of phase changes of a set of clocks into a set of input circuits; wherein the set of phase changes are either falling phase changes or rising phase changes; wherein two phase changes of the set of clocks are fed into each input circuit of the set of input circuits, determining for each input circuit of the set of input circuits a duty cycle, storing the duty cycle for each input circuit of the input circuits in a set of duty cycles, calculating skew between the set of clocks using the duty cycles, and adjusting a delay to lower the skew between the set of clocks.

Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

An image sensor includes image sensor cells generating an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes charge pump cells to receive clock signals and to source charge to the first power supply node, a delay line including delay line elements generating clock signals, where a first charge pump cell receives a first clock signal generated by a first delay line element, where a second charge pump cell receives a second clock signal generated by a second delay line element, and where a delay between the first clock signal and the second clock signal is determined by the delay line.

A semiconductor device includes a plurality of pulse width modulation circuits, wherein the respective pulse width modulation circuits include a first inverter for inverting clock signals and outputting a first inversion signal, a NOR gate for performing a NOR operation on the first inversion signal and a first logic signal and outputting a second logic signal, and a second inverter for inverting the second logic signal and outputting a second inversion signal. Regarding two adjacent pulse width modulation circuits from among the pulse width modulation circuits, a clock signal of one pulse width modulation circuit is delayed from a clock signal of the other pulse width modulation circuit from among the pulse width modulation circuits by a predetermined phase, and the first logic signal of the one pulse width modulation circuit is the second logic signal of the other pulse width modulation circuit.

A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.

Multiple, distributed, clock generating delay-locked loop (DLL) elements are interconnected/coupled in such a way as to reduce the amount of phase error present in the clocks output by these DLL elements. A plurality of DLL elements are interconnected/coupled such that a root input clock is successively relayed down a series of DLL elements. The output clocks from each of these DLL elements are interconnected/coupled to phase-corresponding output clocks from DLL elements in the series. This reduces the amount of phase error on these output clocks when compared to DLL elements that do not have outputs coupled to each other.

The invention proposes a method for distributing a signal to each block B.sub.j of a series of N adjacent blocks of identical design in an electronic circuit. It proposes, in an identical fashion for each of the N blocks, placing a timing delay circuit MUX-DEL.sub.j on the path for conveying a signal S.sub.c from the input INc.sub.j of the block to an internal electrical node Nd.sub.j of the block for this signal S.sub.c; providing for the timing delay circuit to supply N delayed signals corresponding to N different timing delays Δf.sub.1 , . . . Δf.sub.j, . . . Δf.sub.N separated by an increment of elementary duration Δt that corresponds to the elementary delay Δt for transit of a block introduced into a conductive line; and selecting the delayed signal corresponding to the applicable timing delay according to the block in question, by means of an index signal propagated through the N blocks, and which is incremented or decremented on passage through each block.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.