A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.

The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.

An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.

An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result.

An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result.

Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.