A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

Some examples relate to a frequency synthesizer. The frequency synthesizer includes an oscillator including an input terminal and an output terminal. A frequency locked-loop or phase-locked loop (FLL/PLL) unit is arranged on a feedback path extending between the output terminal of the oscillator and the input terminal of the oscillator. A switching unit is configured to selectively switch between a first mode of operation in which the feedback path is closed and the FLL/PLL unit is coupled to the input terminal of the oscillator, and a second mode of operation in which the feedback path is open and a ramping unit is coupled to the input terminal of the oscillator while the feedback path is open.

A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.

The present disclosure discloses a digital loop filter in an all-digital phase-locked loop. The digital loop filter may include a selection circuit configured to output one of a first data signal and a second data signal as valid data, a first operation circuit configured to output a first operation signal by adding or subtracting the valid data and a first register signal, a first register circuit configured to register the first operation signal and output the first operation signal as the first register signal, a second operation circuit configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and a second register circuit configured to store the second operation signal and output the second operation signal as a control signal.

A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.