A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, first input is connected to the comparator output, the second inputs is connected to the second amplifier output; a sampling capacitor connected between the second input of the first amplifier and a ground; and an integration capacitor connected between the comparator output and the ground.

An oscillator drive circuit and a trim circuit are implemented inside an integrated circuit of a sensor. The drive circuit provides an oscillating drive signal at a resonant frequency to drive a movable mass of the sensor. The drive circuit includes a phase shift circuit having an input for receiving a first signal indicative of an oscillation of the movable mass and having an output. The phase shift circuit adds a phase shift component to the first signal and produces a second signal shifted in phase by the phase shift component. The trim circuit includes a first comparator for receiving the first signal, a second comparator for receiving the second signal, and a processing element. The processing element determines a phase lag between the first and second signals and produces trim code for use by the phase shift circuit, the trim code being configured to adjust the phase shift component.

A closed-loop control device to control a system to be controlled includes a front node, back node, external tapping point, controller and compensating circuit. The compensating circuit has an inner node, frequency filter, front buffer and back buffer. The front node determines a difference; the back node supplies an external sum signal. A setting device automatically suppresses use of the output signal of the front buffer, supplies the back buffer and the back node with a first excitation signal as the compensation signal and detects a first result signal produced by the first excitation signal. The first result signal is one of the control difference, internal sum signal, output filtered signal of the frequency filter or output signal of the front buffer. The setting device evaluates the first excitation signal and the first result signal, sets a parameter of the frequency filter and the second propagation delay.

A closed-loop control device to control a system to be controlled includes a front node, back node, external tapping point, controller and compensating circuit. The compensating circuit has an inner node, frequency filter, front buffer and back buffer. The front node determines a difference; the back node supplies an external sum signal. A setting device automatically suppresses use of the output signal of the front buffer, supplies the back buffer and the back node with a first excitation signal as the compensation signal and detects a first result signal produced by the first excitation signal. The first result signal is one of the control difference, internal sum signal, output filtered signal of the frequency filter or output signal of the front buffer. The setting device evaluates the first excitation signal and the first result signal, sets a parameter of the frequency filter and the second propagation delay.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

A semiconductor device includes a clock generator which receives an input clock and generates an output clock, a reference voltage generator which receives the input clock or the output clock, generates a sub-reference voltage in accordance with a frequency of the input clock or a frequency of the output clock, and generates a reference voltage using the sub-reference voltage and a preset error voltage, and a clock detector which receives the output clock, generates a first output voltage in accordance with the output clock, and compares the generated first output voltage with the reference voltage to output an error signal based on the output clock, wherein the preset error voltage is set in accordance with a degree of preset error of the output clock.

A semiconductor device includes a clock generator which receives an input clock and generates an output clock, a reference voltage generator which receives the input clock or the output clock, generates a sub-reference voltage in accordance with a frequency of the input clock or a frequency of the output clock, and generates a reference voltage using the sub-reference voltage and a preset error voltage, and a clock detector which receives the output clock, generates a first output voltage in accordance with the output clock, and compares the generated first output voltage with the reference voltage to output an error signal based on the output clock, wherein the preset error voltage is set in accordance with a degree of preset error of the output clock.