A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more

Disclosed is a temperature-compensated crystal oscillator based on analog circuit; a closed-loop compensation architecture determines the temperature compensation of a crystal oscillator. The power splitter divides the VCXO's current output signal with frequency f=f.sub.0+Δf into two signals, one signal to output of the TCXO and the other signal is sent to an analog frequency-voltage conversion circuit. According to the frequency of the VCXO's current output signal, the analog frequency-voltage conversion circuit produces a voltage signal V(T), which corresponds to current ambient temperature. The difference between V(T) and a reference voltage signal V.sub.ref is produced and amplified to obtain a compensation voltage signal ΔV through a voltage matching circuit. ΔV is smoothed by a filter, then sent to the voltage control terminal of the VCXO to make the VCXO generate a stable signal with desired frequency f.sub.0, to compensate the frequency of the VCXO's output signal when the ambient temperature is changed.

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Circuits, systems and computer readable media transmission of wireless signals in response to incoming signals in a wireless signaling environment. Such a system may include at least one transceiver for receiving an incoming signal via an antenna array from a device in the wireless signaling environment. The system may also include a controller operably coupled to the transceiver. The controller may measure a phase of the incoming signal, and determine, based on the phase, a transmit phase configuration for one or more antennas of the antenna array. The system may include at least one phase-locked loop (PLL) operably coupled to the transceiver(s). The PLL(s) may feed signals to the antenna(s) of the antenna array based on the transmit phase configuration for transmission of a responsive signal to the device.

Circuits, systems and computer readable media transmission of wireless signals in response to incoming signals in a wireless signaling environment. Such a system may include at least one transceiver for receiving an incoming signal via an antenna array from a device in the wireless signaling environment. The system may also include a controller operably coupled to the transceiver. The controller may measure a phase of the incoming signal, and determine, based on the phase, a transmit phase configuration for one or more antennas of the antenna array. The system may include at least one phase-locked loop (PLL) operably coupled to the transceiver(s). The PLL(s) may feed signals to the antenna(s) of the antenna array based on the transmit phase configuration for transmission of a responsive signal to the device.

A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.