An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

A pulse signal corresponding to rotation of an imaging core is input, and a repetition frequency of the input pulse signal is converted in accordance with the number of radially-aligned lines of an ultrasound tomographic image. Based on the pulse signal of which the repetition frequency has been converted, a drive signal for an ultrasound transceiver is generated to obtain an ultrasound tomographic image with the number of lines. A valid pulse is determined in accordance with the number of lines from the pulse signal of which the repetition frequency has been converted. A signal having a pulse train selected, based on the valid pulse from a pulse signal representing a cycle of a light source of light for interfering with the light from an optical transceiver is generated as a pulse signal representing a timing of sampling of an optical coherence signal for generating an optical tomographic image.

There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

The digital-output temperature sensor includes a temperature sensor circuit, a current mirror circuit which makes a mirror current of a temperature detection current flow and pulls in a mirror current of a reference current to thereby output a first difference current from a first output node and output a second difference current from a second output node, a chopping circuit, and an A/D conversion circuit. The chopping circuit performs a chopping operation of making the mirror current of the reference current flow in a second state through a transistor of the current mirror circuit through which the mirror current of the temperature detection current flows in a first state, and making the mirror current of the temperature detection current flow in the second state through the transistor of the current mirror circuit through which the mirror current of the reference current flows in the first state.

A sensing device includes at least one vibration sensor that responds to sensed vibrations. At least one drive-sense circuit is coupled to the vibration sensor, wherein the at least one drive-sense circuit includes: a first conversion circuit configured to convert a receive signal component of a sensor signal corresponding to the at least one vibration sensor into the sensed signal, wherein the sensed signal indicates a change in an electrical characteristic associated with the at least one vibration sensor; and a second conversion circuit configured to generate, based on the sensed signal, a drive signal component of the sensor signal corresponding to the at least one vibration sensor.

Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.

In modern networks, RRU and BBU equipment of an access point site typically handles traffic from a single sector. An RRU-BBU pair process that traffic (often limited to a single spectrum from a single sector) according to implemented capabilities and other equipment located further upstream perform functions that rely on information from multiple sectors. An integrated device (e.g., white box) can integrate the functionality of multiple RRU (or NR in 5G) and the functionality of multiple BBU (or DU/CU splits in 5G), which can reduce implementation footprint, costs, and can provide related services more efficiently without going upstream.

In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.

A signal processing system for a sensor. The system comprises a digital signal processing system configured to set a drive signal frequency for the primary drive transducer, a voltage controlled oscillator configured to receive an input indicative of the resonant frequency and to generate a first periodic signal at a first multiple of the resonant frequency, and a first phase locked loop, configured to receive the first periodic signal, and to generate a second periodic signal at a second multiple of the resonant frequency. The first and second periodic signals are used to control the operation of an analog-to-digital converter (ADC) configured to sample the primary pick off signal and a digital-to-analog converter (DAC) configured to generate a drive signal waveform applied to the primary drive transducer.

A solar cell power conversion device is disposed between a solar cell and a consumer premises distribution system. A storage battery power conversion device is disposed between a storage battery and the consumer premises distribution system. When an AC effective voltage in the consumer premises distribution system deviates from a voltage range defined in accordance with dead zone information transmitted from HEMS, system voltage stabilization control for returning the AC effective voltage to fall within the voltage range is performed by control of active power and reactive power that are output from a first DC/AC conversion circuit and a second DC/AC conversion circuit.