An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70.sub.j).

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70.sub.j).

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

There is provided an analog-stochastic converter for converting an analog voltage signal into a pulse signal having a corresponding probability. The analog-stochastic converter is implemented using a threshold switching element and a simple logic circuit, thereby reducing a size of the analog-stochastic converter and enabling a low power operation thereof. In addition, in order to update a weight, instead of an analog signal, a probability signal is applied using the above-described analog-stochastic converter, thereby updating a weight in a fully-parallel manner in a synaptic element array having an intersection structure. Accordingly, it is possible to shorten a time for weight update.

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits

Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

Systems and methods are provided for which a chopper modulator and a chopper demodulator of a chopped apparatus having a variable chopper frequency are described. A feedback path is used to reduce ripples and/or remaining offsets as a result of the variable chopper frequency.

In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.