Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.

A circuit for analog-digital conversion, which includes a first connection and a second connection and a third connection and a fourth connection for connecting a sensor, an analog-digital converter (ADC), whose first input is connected to the first connection and whose second input is connected to the second connection, a first current source circuit for outputting a first output current, a first switching device for the switchable connection of the first current source circuit to the first connection or to the third connection, a current source/sink circuit for outputting a second output current, a second switching device for the switchable connection of the current source/sink circuit to a reference potential or to the second connection, and a third switching device for the switchable connection of the reference potential to the second connection or to the fourth connection.

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold.

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

A method of measuring light intensity comprising exposing a photodiode to light to cause the photodiode to provide a current of a first polarity, supplying said current to an integrator to integrate said current to provide an integrated output voltage, and comparing the output voltage with a threshold voltage. Charge packages of opposite polarity are applied to said first polarity to reset the integration voltage prior to the start of the integration time. At the end of the integration time, the photodiode is disconnected from said integrator and a reference voltage coupled to the integrator input, whilst a resistance is coupled into the circuit until the comparison signal switches. The comparison signal is monitored to measure a time between the end of the integration time and the switching of the comparison signal to provide a measure of a residual voltage.

An input stage for an analog/digital converter, an analog/digital converter and a method for testing analog/digital converters with successive approximation are disclosed. At an input stage, an input signal is supplied via a first transistor arrangement of a sampling capacitor arrangement. The sampling capacitor arrangement can be optionally connected to ground or to a reference voltage by way of a second transistor arrangement and a switch apparatus.

An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.